SEMICONDUCTIVE DEVICE AND ASSOCIATED METHOD OF MANUFACTURE

• US 20150333133A1
• Filed: 04/22/2015
• Published: 11/19/2015
• Est. Priority Date: 05/14/2014
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Boettcher, Tim, Behtash, Reza, Igel-Holtzendorff, Thomas, Zhu, Linpei
• Granted Patent: US 9,911,816 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

The disclosure relates to a semiconductive device comprising a body having: a first surface and an opposing second surface; a first semiconductive layer adjacent to the first surface; an active region comprising: a plurality of active trenches in the first surface, the plurality of active trenches extending from the first surface into the first semiconductive layer and having an active trench width, and a plurality of active cells, each active cell provided in the first semiconductive layer adjacent to an active trench, the active cells having an active cell width; and a termination region at a periphery of the first surface comprising: at least one termination trench, the at least one termination trench extending from the first surface into the first semiconductive layer, wherein the termination region has a width that is greater than the active trench width; and a number of termination trench separators having a width that is less than the active cell width, wherein the active trenches and the at least one termination trench each comprise a first insulator layer adjacent to the first semiconductive layer of the body, and wherein conductive material is disposed on the first insulating layer within each of the active trenches.

Claims

1. A semiconductive device comprising a body having:

a first surface and an opposing second surface;

a first semiconductive layer adjacent to the first surface;

an active region comprising;

a plurality of active trenches in the first surface, the plurality of active trenches extending from the first surface into the first semiconductive layer and having an active trench width, and

a plurality of active cells, each active cell provided in the first semiconductive layer adjacent to an active trench, the active cells having an active cell width; and

a termination region at a periphery of the first surface comprising;

at least one termination trench, the at least one termination trench extending from the first surface into the first semiconductive layer, and

a number of termination trench separators having a width that is less than the active cell width, wherein the termination region has a width that is greater than the active trench width,

wherein the active trenches and the at least one termination trench each comprise a first insulator layer adjacent to the first semiconductive layer of the body, and wherein conductive material is disposed on the first insulating layer within each of the active trenches.

2. The semiconductive device of claim 1, wherein the number of termination trench separators is zero and the width of the termination trench is equal to the width of the termination region.

3. The semiconductive device of claim 1, wherein the body comprises a plurality of termination trenches.

4. The semiconductive device of claim 2, wherein the at least one termination trench has a width across the first surface that is greater than the width of the active trench.

5. The semiconductive device of claim 1, wherein a first electrically conductive layer extends over substantially all of the active region and the termination region.

6. The semiconductive device of claim 1, wherein the body comprises a second insulating layer disposed on material in the at least one termination trench.

7. The semiconductive device of claim 6, comprising a first electrically conductive layer on the first surface that connects the active cells between the active trenches and extends over the second insulating layer.

8. The semiconductive device of claim 1 wherein the conductive material comprises poly-silicon or a metal.

9. The semiconductive device of claim 1, wherein the at least one termination trench is completely filled with conductive material within the first oxide layer.

10. The semiconductive device of claim 1, wherein the body has a second semiconductive layer adjacent to the second surface, the first semiconductive layer having a different conductivity to the second semiconductive layer.

11. The semiconductive device of claim 10, comprising a second electrically conductive layer disposed on the second surface.

12. The semiconductive device of claim 1, wherein the active trenches have a depth that extends from the first surface into the first semiconductive layer and terminate in the first semiconductive layer.

13. The semiconductive device of claim 1, wherein the depth of the active trenches is the same as a depth of the at least one termination trench.

14. A method of manufacturing a semiconductive device, comprising:

providing a body having first surface, an opposing second surface and a first semiconductive layer adjacent to the first surface within the body;

providing an active region comprising a plurality of active trenches extending from the first surface into the first semiconductive layer and having an active trench width, wherein the active trenches define a plurality of active cells in the active region, each active cell provided in the first semiconductive layer adjacent to an active trench and having an active cell width;

providing a termination region at a periphery of the first surface, the termination region comprising;

at least one termination trench extending from the first surface into the first semiconductive layer, and

a number of termination trench separators having a width that is less than the active cell width, the termination region having a width that is greater than the active trench width;

forming a first insulator layer adjacent to the first semiconductive layer in the active trenches and the at least one termination trench;

disposing conductive material within the first insulating layer in the active trenches.

15. A semiconductor fabrication apparatus configured to perform the method of claim 14.