DUAL FILL SILICON-ON-NOTHING FIELD EFFECT TRANSISTOR

• US 20150333167A1
• Filed: 05/19/2014
• Published: 11/19/2015
• Est. Priority Date: 05/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi
• Granted Patent: US 9,548,358 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a substrate. After formation of a first dielectric isolation layer around the patterned stack, a disposable gate structure can be formed. End portions of the second silicon-germanium alloy nanowire are removed to form first cavities underlying end portions of the silicon-containing nanowire. Dielectric nanowires are formed in cavities concurrently with formation of a gate spacer. After recessing the first dielectric isolation layer, a second cavity is formed by removing the first silicon-germanium alloy nanowire. The second cavity is filled with a second dielectric isolation layer, and raised active regions can be formed by a selective epitaxy process. After formation of a planarization dielectric layer, the disposable gate structure and the remaining portion of the second silicon-germanium alloy nanowire with a replacement gate structure.

Claims

1. A semiconductor structure comprising:

at least one dielectric isolation layer located on a substrate;

a silicon-containing nanowire overlying said at least one dielectric isolation layer;

a pair of dielectric nanowires laterally spaced from each other, and contacting a bottom surface of said silicon-containing nanowire and a top surface of said at least one dielectric isolation layer; and

a gate structure including a gate dielectric and a gate electrode, said gate structure encircling a portion of said silicon-containing nanowire.

2. The semiconductor structure of claim 1, wherein said pair of dielectric nanowire is laterally spaced from each other by a portion of said gate structure that underlies said silicon-containing nanowire.

3. The semiconductor structure of claim 2, wherein a combination of said pair of dielectric nanowires and said portion of said gate structure that underlies said silicon-containing nanowire has a same horizontal cross-sectional area as said silicon-containing nanowire.

4. The semiconductor structure of claim 1, wherein said at least one dielectric isolation layer comprises:

a first dielectric isolation layer located on a substrate and including at least one rectangular opening therethrough; and

a second dielectric isolation layer contacting a top surface of said first dielectric isolation layer and including a recessed portion that fills said at least one opening.

5. The semiconductor structure of claim 4, wherein said silicon-containing nanowire overlies, and has a same horizontal cross-sectional area as, said recessed portion of said second dielectric isolation layer.

6. The semiconductor structure of claim 4, wherein said pair of dielectric nanowires contacts a top surface of said recessed portion.

7. The semiconductor structure of claim 6, wherein a combination of said pair of dielectric nanowires and said portion of said gate structure that underlies said silicon-containing nanowire has a same horizontal cross-sectional area as said recessed portion.

8. The semiconductor structure of claim 4, wherein a topmost surface of said first dielectric isolation layer is located between a horizontal plane including a bottommost surface of said second dielectric isolation layer and another horizontal plane including a topmost surface of said second dielectric isolation layer, and a bottommost surface of said first dielectric isolation layer is located below said horizontal plane including said bottommost surface of said second dielectric isolation layer.

9. The semiconductor structure of claim 1, wherein each of said pair of dielectric nanowires has an end wall that is vertically coincident with an end wall of said silicon-containing nanowire.

10. The semiconductor structure of claim 1, further comprising a gate spacer laterally surrounding an upper portion of said gate structure and comprising a same dielectric material as said pair of dielectric nanowires.

11. A method of forming a semiconductor structure comprising:

forming a stack including, from bottom to top, a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire on a substrate;

forming a first dielectric isolation layer around said stack and over said substrate;

forming a gate structure across said stack;

forming first cavities by removing end portions of said second silicon-germanium alloy nanowire while a portion of said second silicon-germanium alloy nanowire underlying said gate structure is not removed;

forming a pair of dielectric nanowires in said first cavities;

forming a second cavity by removing said first silicon-germanium alloy nanowire from underneath said pair of dielectric nanowires; and

filling said second cavity with a second dielectric isolation layer.

12. The method of claim 11, wherein a topmost surface of said first dielectric isolation layer is between a first horizontal plane including a top surface of said second silicon-germanium alloy nanowire and a second horizontal plane including a bottom surface of said second silicon-germanium alloy nanowire while said first cavities are formed.

13. The method of claim 12, further comprising recessing said topmost surface of said first dielectric isolation layer to a height between said second horizontal plane and a third horizontal plane including a bottom surface of said first silicon-germanium alloy nanowire prior to forming said second cavity.

14. The method of claim 11, wherein said first silicon-germanium alloy nanowire has a greater atomic concentration of germanium than said second silicon-germanium alloy nanowire.

15. The method of claim 11, further comprising removing said portion of said second silicon-germanium alloy nanowire selective to said silicon-containing nanowire and said pair of dielectric nanowires after filling said cavity with said second dielectric isolation layer.

16. The method of claim 11, further comprising forming a gate spacer around said gate structure simultaneously with formation of said pair of dielectric nanowires by deposition of a dielectric material layer and a subsequent anisotropic etch.

17. The method of claim 11, further comprising forming raised active regions by a selective epitaxy process on physically exposed surfaces of said silicon-containing nanowire after formation of said second dielectric isolation layer.

18. The method of claim 17, further comprising forming a planarization dielectric layer over said raised active regions and directly on a surface of said second dielectric isolation layer.

19. The method of claim 18, wherein said gate structure is a disposable gate structure, and said method further comprises:

forming a gate cavity at least by removing said disposable gate structure selective to said planarization dielectric layer, said silicon-containing nanowire, and said first dielectric isolation layer; and

forming a replacement gate structure in said gate cavity.

20. The method of claim 19, further comprising extending said gate cavity by removing said portion of said second silicon-germanium alloy nanowire selective to said silicon-containing nanowire and said pair of dielectric nanowires before forming said replacement gate structure.