SPLIT GATE MEMORY DEVICES AND METHODS OF MANUFACTURING

• US 20150333173A1
• Filed: 05/13/2014
• Published: 11/19/2015
• Est. Priority Date: 05/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Liu, Shih-Chang, Tsai, Chia-Shiung, Lee, Ru-Liang
• Granted Patent: US 9,748,255 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device.

Claims

1. A memory device, comprising:

a semiconductor substrate comprising first and second source/drain regions, which are separated from one another by a channel region;

a floating gate arranged over the channel region, wherein the floating gate has an upper surface with a first width and wherein a first dielectric separates the floating gate from the channel region;

a control gate arranged over the floating gate, wherein the control gate has a lower surface with a second width that is less than the first width, and wherein a second dielectric separates the control gate from the floating gate; and

first and second spacers formed along sidewalls of the control gate and arranged over outer edges of the floating gate upper surface, wherein lower sidewall regions of the first and second spacers taper down towards a neck region within the floating gate, wherein the neck region comprises a third width that is less than the second width of the upper surface.

2. The memory device of claim 1, further comprising:

an erase gate arranged over the first source/drain region, the erase gate configured to promote tunneling of electrons from the floating gate into the erase gate; and

a tunneling dielectric layer that extends over sidewalls of the floating gate to separate the erase gate from the floating gate.

3. The memory device of claim 2, wherein the tunneling dielectric layer has a uniform thickness between the erase gate and the floating gate.

4. The memory device of claim 1, wherein:

the control gate is narrower than the floating gate, such that floating gate upper surface regions extend outwardly past edges of the control gate;

the first and second spacers are formed over the floating gate upper surface; and

a silicon nitride hardmask is formed over the control gate.

5. The memory device of claim 4, wherein the first and second spacers comprise:

a spacer dielectric layer comprising a horizontal portion that extends over the floating gate upper surface, and a vertical portion that extends along sidewalls of the control gate and silicon nitride hardmask; and

a spacer nitride layer formed over the horizontal portion of the spacer dielectric layer, which extends vertically adjacent the vertical portion of the spacer dielectric layer.

6. The memory device of claim 5, further comprising a high-temperature oxide (HTO) layer that separates the spacer dielectric layer from the floating gate, control gate, and silicon nitride hardmask.

7. The memory device of claim 6, wherein the HTO layer comprises a horizontal portion that extends over the upper surface of the floating gate, and a vertical portion that extends along sidewalls of the control gate and silicon nitride hardmask.

8. A memory device, comprising:

a semiconductor substrate comprising first and second source/drain regions, which are separated from one another by a channel region;

a floating gate arranged over the channel region, wherein the floating gate has an upper surface with a first width and wherein a first dielectric separates the floating gate from the channel region;

a control gate arranged over the floating gate, wherein the control gate has a lower surface with a second width that is greater than the first width, and wherein a second dielectric layer separates the control gate from the floating gate; and

an erase gate formed over the first source/drain region, which resides laterally adjacent the floating gate;

wherein a height of the control gate tapers in a direction of the erase gate such that a top surface of the control gate diagonally-abuts the second dielectric layer at an interface to a sidewall of the floating gate.

9. The memory device of claim 8, wherein the top surface of the control gate, surface of the second dielectric layer, and the sidewall of the floating gate form a smooth continuous surface at the interface.

10. The memory device of claim 8, further comprising a select gate formed over the second source/drain region, which resides laterally adjacent the floating gate, opposite the erase gate.

11. The memory device of claim 10, wherein the control gate comprises a horizontal portion that extends over a top surface of the floating gate, and a vertical portion that extends along a sidewall of the floating gate to isolate the floating gate from the select gate.

12. The memory device of claim 10, wherein the control gate comprises a horizontal portion that extends over a top surface of the floating gate, and first and second sidewalls of the floating gate are isolated from the select gate and the control gate, respectively, by an insulating layer.

13. A method of forming a memory device, comprising:

forming a floating gate over a channel region of a substrate, wherein the channel region separates first and second source/drain regions from one another;

forming a control gate over the floating gate, wherein a first width of the control gate is less than a second width of the floating gate;

forming first and second spacers along sidewalls of the control gate, the first and second spacers extending over outer edges of an upper surface of the floating gate; and

performing an etching process on first and second spacers, which removes a portion of the first and second spacers that extends over the outer edges of an upper surface of the floating gate at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface.

14. The method of claim 13, wherein the etching process removes lower sidewall regions of the first and second spacers such that the first and second spacers taper down towards a neck region within the floating gate.

15. The method of claim 14, wherein the etching process comprises an argon sputter or ion beam etch.

16. The method of claim 15, wherein the argon sputter or ion beam etch is performed at an angle between about 30°

and 50°

relative to a normal vector to a surface of the substrate.

17. A method of forming a memory device, comprising:

forming a floating gate over a channel region of a substrate, wherein the channel region separates first and second source/drain regions from one another;

forming a control gate over the floating gate, wherein a first width of the control gate is greater than a second with of the floating gate such that the control gate extends over an outer edge of an upper surface of the floating gate; and

performing an angled etching process on the control gate, which removes a portion of the control gate that extends over the outer edge of the upper surface of the floating gate at an interface between a top surface of the control gate and a sidewall of the floating gate.

18. The method of claim 17, wherein:

the control gate is separated from the floating gate by a second dielectric;

the etching process tapers a height of the control gate, such that the top surface of the control gate diagonally-abuts the second dielectric at the interface to the sidewall of the floating gate; and

the top surface of the control gate, surface of the second dielectric, and the sidewall of the floating gate form a smooth continuous surface at the interface.

19. The method of claim 17, wherein the etching process is performed at an angle between about 30°

and 50°

with a normal vector to a surface of the substrate.

20. The method of claim 17, wherein the etching process comprises an argon sputter or ion beam etch.