HIGH SPEED, RAIL-TO-RAIL CMOS DIFFERENTIAL INPUT STAGE

• US 20150333705A1
• Filed: 07/28/2014
• Published: 11/19/2015
• Est. Priority Date: 05/15/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments Deutschland Gesellschaft Mit Beschrã¤Nkter Haftung (Texas Instruments, Inc.)
• Inventors: Rombach, Gerd
• Granted Patent: US 9,356,570 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2203/45066 the resulting deducted common mode signal being added at the one or more inputs of the differential amplifier
• CPC Class Codes: H03F 2203/45116 Feedback coupled to the input of the differential amplifier
• CPC Class Codes: H03F 3/3022 CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series

Abstract

An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output., wherein the differential input controlled by transistors P1-3 and N1-N3; and a means for weighting (sizing) of transistor (P1 & P3) relative to P2 and (N1 & N3) relative to N2 defines the optimal operation mode.

Claims

1. An apparatus, comprising:

a differential input stage with signals IN_P &

IN_N as input and OUT_P &

OUT_N as output.

2. The apparatus of claim 1, further comprising a differential input controlled by transistors P1-3 and N1-N3.

3. The apparatus of claim 1, further comprising weighting (sizing) of transistor (P1 &

P3) relative to P2 and (N1 &

N3) relative to N2 defines the optimal operation mode.

4. The apparatus of claim 1, further comprising a Half input replica with ‘

Vthreshold’

predefines the common mode input voltage.

5. The apparatus of claim 4, wherein the apparatus comprises an Op-amp that controls the output of the half input replica to be ‘

inv_bias’

.

6. The apparatus of claim 1, wherein an output inverter replica (INV2) controls the biasing of to driver INV0 and INV1.

7. An apparatus, comprising:

a single-ended input stage with signals IN_P &

IN_N as input and OUT_P &

OUT_N as output.

8. The apparatus of claim 7, further comprising a differential input controlled by transistors P1-3 and N1-N3.

9. The apparatus of claim 7, further comprising a means for weighting (sizing) of transistor (P1 &

P3) relative to P2 and (N1 &

N3) relative to N2 defines the optimal operation mode.

10. The apparatus of claim 7, further comprising a Half input replica with ‘

Vthreshold’

predefines the common mode input voltage.

11. The apparatus of claim 10, wherein the apparatus comprises an Op-amp that controls the output of the half input replica to be ‘

inv_bias’

.

12. The apparatus of claim 7, wherein an output inverter replica (INV2) controls the biasing of to driver INV0 and INV1.

14. The apparatus of claim 7, further comprising a Half input replica with ‘

Vthreshold’

predefines the common mode input voltage.

15. The apparatus of claim 10, wherein the apparatus comprises an Op-amp that controls the output of the half input replica to be ‘

inv_bias’

.

16. The apparatus of claim 7, wherein an output inverter replica (INV2) controls the biasing of to driver INV0 and INV1.

13. An apparatus, comprising:

a single-ended input stage with signals IN_P &

IN_N as input and OUT_P &

OUT_N as output,

wherein the differential input controlled by transistors P1-3 and N1-N3; and

a means for weighting (sizing) of transistor (P1 &

P3) relative to P2 and (N1 &

N3) relative to N2 defines the optimal operation mode.