DATA TRANSFER CLOCK RECOVERY FOR LEGACY SYSTEMS

• US 20150333902A1
• Filed: 07/24/2015
• Published: 11/19/2015
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Robertson, Iain, Williams, Richard
• Granted Patent: US 9,419,788 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate serial data, the receiver having a jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the SERDES receiver for frame realignment; and supplying to an output of the SERDES receiver one of the bits of said same value from each frame at the low data rate.

Claims

1. A deserializer circuit comprising:

a sampler circuit configured to receive a stream of bits transmitted at a transmission rate and sample the received stream of bits at a reception rate higher than the transmission rate;

a symbol assembly circuit coupled with the sampler circuit, and configured to group a portion of the sampled stream of bits into a frame; and

a bit alignment circuit coupled with the symbol assembly circuit, and the bit alignment circuit configured to detect a frame slip when two sampled bits within the frame have different values, and upon detecting the frame slip, the bit alignment circuit configured to realign the frame until the two sampled bits share a same bit value.

2. The deserializer circuit of claim 1, wherein the reception rate is at least 10 times of the transmission rate.

3. The deserializer circuit of claim 1, wherein the bit alignment circuit is configured to supply the same bit value of the two sampled bits as a data bit output of the received stream of bits.

4. The deserializer circuit of claim 1, wherein the bit alignment circuit includes:

a data frame register configured to receive the frame of sampled bits from the symbol assembly circuit, the data frame register having a mid-frame bit and a peripheral bit configured to store the two sampled bits of the received frame; and

a comparator circuit coupled with the data frame register to receive the mid-frame bit and the peripheral bit, the comparator circuit configured to generate a jog signal when the mid-frame bit is different from the peripheral bit, the jog signal causing the data frame register to realign the frame.

5. The deserializer circuit of claim 4, wherein the comparator circuit includes a NOR gate having a first input coupled to the mid-frame bit of the data frame register, and a second input coupled to the peripheral bit of the data frame register.

6. The deserializer circuit of claim 4, wherein the frame has 10 sampled bits including a fifth bit assigned as the mid-frame bit, and an eighth bit assigned as the peripheral bit.

7. The deserializer circuit of claim 4, wherein the mid-frame bit and the peripheral bit is separated by one-third of the frame of sampled bits.

8. The deserializer circuit of claim 1, wherein the bit alignment circuit is configured to realign the frame by shifting the frame by one-tenth of a length of the frame.

9. The deserializer circuit of claim 1, wherein:

the frame has 10 sampled bits including a first bit and a tenth bit received after the first bit, and

the bit alignment circuit is configured to realign the frame by shifting the frame towards the first bit.

10. The deserializer circuit of claim 1, wherein:

the frame has 10 sampled bits including a first bit and a tenth bit received after the first bit, and

the bit alignment circuit is configured to realign the frame by increasing the frame to include a zeroth bit received before the first bit.

11. The deserializer circuit of claim 1, wherein the sampler circuit is configured to drift the sampled stream of bits by a magnitude greater than an expected jitter of the received stream of bits.

15. The deserializer circuit of claim 4, wherein the mid-frame bit and the peripheral bit is separated by one-third of the frame length.

16. The deserializer circuit of claim 1, wherein the data frame register is configured to realign the frame by shifting the frame by one-tenth of the frame length.

12. A deserializer circuit comprising:

a symbol assembly circuit configured to collect a stream of received bits into a frame having a frame length of bits; and

a bit alignment circuit including;

a data frame register coupled with the symbol assembly to receive the frame of received bits, the data frame register having a mid-frame bit and a peripheral bit configured to store two received bits of the frame length of bits; and

a comparator circuit coupled with the data frame register to receive the mid-frame bit and the peripheral bit, the comparator circuit configured to generate a jog signal when the mid-frame bit is different from the peripheral bit, the jog signal causing the data frame register to realign the frame.

13. The deserializer circuit of claim 12, wherein:

the comparator circuit is configured to detect the mid-frame bit and the peripheral bit share a same data bit; and

upon detecting the same data bit, the data frame register is configured to deliver the same data bit as an output data bit of the stream of received bits.

14. The deserializer circuit of claim 12, wherein the comparator circuit includes a NOR gate having a first input coupled to the mid-frame bit of the data frame register, and a second input coupled to the peripheral bit of the data frame register.

17. A bit alignment circuit for use in a deserializer configured to sample a stream of bits, the bit alignment circuit comprising:

a data frame register configured to store a frame length of sampled bits having a mid-frame bit and a peripheral bit; and

a comparator circuit coupled with the data frame register to receive the mid-frame bit and the peripheral bit, the comparator circuit configured to generate a jog signal when the mid-frame bit is different from the peripheral bit, the jog signal causing the data frame register to realign the frame until the mid-frame bit and the peripheral bit share a same bit value.

18. The bit alignment circuit of claim 17, wherein the comparator circuit includes a NOR gate having a first input coupled to the mid-frame bit of the data frame register, and a second input coupled to the peripheral bit of the data frame register.

19. The deserializer circuit of claim 17, wherein the mid-frame bit and the peripheral bit is separated by one-third of the frame length.

20. The deserializer circuit of claim 17, wherein the bit alignment circuit is configured to realign the frame by shifting the frame by one-tenth of the frame length.