CODED INTEGRATION OF A SELF-CAPACITANCE ARRAY

• US 20150338952A1
• Filed: 05/23/2014
• Published: 11/26/2015
• Est. Priority Date: 05/23/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: SHAHPARNIA, Shahrooz, YOUSEFPOR, Marduke
• Granted Patent: US 10,558,302 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes

Abstract

Coded integration of a self-capacitance array to improve signal-to-noise ratio (SNR) of self-capacitance measurements is disclosed. A composite measurement of the self-capacitance of a plurality of electrodes can be measured for a plurality of integration periods. The composite measurements can include weighted contributions of charge from the plurality of electrodes, the weighting corresponding to a code. In some examples, the weighted contribution can include positive contributions integrated by a first integrator circuit and negative contributions integrated by a second integrator circuit. The composite measurements of the self-capacitance for the plurality of integration periods can be decoded to extract the self-capacitance measurement for the electrodes. The SNR for the self-capacitance measurements can therefore be improved by increasing the number of samples during the total integration period without requiring dedicated sensing circuitry for the electrodes.

Claims

1. A method for measuring a self-capacitance of a plurality of electrodes, the method comprising:

coupling the plurality of electrodes to a sense channel during a plurality of integration periods, wherein at least two of the plurality of electrodes are simultaneously coupled to the sense channel during at least one of the plurality of integration periods;

generating a plurality of composite output signals, one or more of the plurality of composite output signals based on an output of the sense channel during a corresponding integration period; and

demodulating the plurality of composite output signals to extract a self-capacitance measurement for the plurality of electrodes.

2. The method of claim 1, further comprising:

integrating a first input signal comprising signal contributions from one or more of the plurality of electrodes coupled to an input of a first integrator circuit; and

integrating a second input signal comprising signal contributions from one or more of the plurality of electrodes coupled to an input of a second integrator circuit.

3. The method of claim 2, wherein an output of the first integrator circuit corresponds to a positive contribution of the first input signal and an output of the second integrator circuit corresponds to a negative contribution of the second input signal.

4. The method of claim 2, wherein the first and second integrator circuits are implemented using two single-ended operational amplifiers.

5. The method of claim 2, wherein the first and second integrator circuits are implemented using a differential operational amplifier and the first and second input signals are integrated differentially.

6. The method of claim 1, wherein the sense channel comprises a leaky integrator circuit.

7. The method of claim 2, wherein the plurality of electrodes are coupled to the input of the first integrator circuit or the input of the second integrator circuit via one or more switches.

8. The method of claim 2, wherein the coupling of the plurality of electrodes during the plurality of integration periods is coded based on a value of a plurality of values stored in memory.

9. The method of claim 8, wherein an electrode is coupled to the first integrator circuit during an integration period if the value of the plurality of values corresponding to the electrode and the integration period is 1 and the electrode is coupled to the second integrator circuit during the integration period if the value of the plurality of values corresponding to the electrode and the integration period is −

1.

10. The method of claim 8, wherein the plurality of values are selected such that a matrix formed of the plurality of values, arranged such that a first dimension of the matrix corresponds to the plurality of integration periods and a second dimension of the matrix corresponds to the plurality of electrodes, is invertible and has a gain greater than unity.

11. The method of claim 10, wherein the plurality of values correspond to entries of a Hadamard matrix of an order equal to a total number of electrodes in the plurality of electrodes.

12. The method of claim 1, further comprising:

generating a first composite output signal corresponding to a first voltage reference;

generating a second composite output signal corresponding to a second voltage reference; and

subtracting the second composite output signal from the first composite output signal to remove noise.

13. The method of claim 2, wherein generating the plurality of composite output signals further comprises subtracting an output of the second integrator circuit from an output of the first integrator circuit.

14. The method of claim 8, wherein demodulating the plurality of composite output signals comprises decoding the self-capacitance measurement for the plurality of electrodes based on an inverse of the plurality of values.

15. The method of claim 1, further comprising:

integrating a first input signal comprising signal contributions from one or more of the plurality of electrodes coupled to the input of an integrator circuit during a first portion of an integration period;

integrating a second input signal comprising signal contributions from one or more of the plurality of electrodes coupled to the input of the integrator circuit during a second portion of the integration period; and

generating a composite output signal based on the difference between an output of the integrator circuit during the first portion of the integration period and the output of the integrator circuit during the second portion of the integration period.

16. An apparatus for measuring self-capacitance, the apparatus comprising:

sensing circuitry configured to be coupled to a plurality of electrodes via a plurality of switches;

logic configurable to control the plurality of switches to couple the plurality of electrodes to the sensing circuitry, wherein the plurality of switches can be controlled to simultaneously couple the sensing circuitry to at least two of the plurality of electrodes; and

a demodulation section configurable to decode a plurality of outputs of the sensing circuitry to determine the self-capacitance of the plurality of electrodes.

17. The apparatus of claim 16, wherein the sense circuitry comprises a first integrator circuit and a second integrator circuit and the plurality of switches configurable to couple the plurality of electrodes to an input of the first integrator circuit or an input of the second integrator circuit.

18. The apparatus of claim 17, wherein the first and second integrator circuits are implemented using two single-ended operational amplifiers.

19. The apparatus of claim 17, wherein the first and second integrator circuits are implemented using a differential operational amplifier.

20. The apparatus of claim 16, wherein the sensing circuitry comprises a leaky integrator circuit.

21. The apparatus of claim 17, wherein the sensing circuitry further comprises a differential analog-to-digital converter (ADC), and an output of the first integrator circuit is coupled to a first input of the differential ADC and an output of the second integrator circuit is coupled to a second input of the differential ADC.

22. The apparatus of claim 17, wherein the first integrator circuit integrates a first input signal comprising signal contributions from one or more of the plurality of electrodes coupled to the input of the first integrator circuit and the second integrator circuit integrates a second input signal comprising signal contributions from one or more of the plurality of electrodes coupled to the input of the second integrator circuit.

23. The apparatus of claim 22, wherein an output of the first integrator circuit corresponds to a positive contribution of the first composite input signal and an output of the second integrator circuit corresponds to a negative contribution of the second composite input signal.

24. The apparatus of claim 17, wherein the logic configurable to control the plurality of switches selects the coupling between the plurality of electrodes and the input of the first or second integrator circuits during a plurality of integration periods based on a value of a plurality of values stored in memory.

25. The apparatus of claim 24, wherein the plurality of values are selected to code signal contributions of the plurality of electrodes.

26. The apparatus of claim 25, wherein the first integrator circuit is configurable to be coupled to an electrode during an integration period if the value of the plurality of values corresponding to the electrode and the integration period is 1 and the second integrator circuit is configurable to be coupled to the electrode during the integration period if the value of the plurality of values corresponding to the electrode and the integration period is −

1.

27. The apparatus of claim 25, wherein the plurality of values are selected such that a matrix formed of the plurality of values, arranged such that a first dimension of the matrix corresponds to a plurality of integration periods and a second dimension of the matrix corresponds to the plurality of electrodes, is invertible and has a gain greater than unity.

28. The apparatus of claim 27, wherein the plurality of values correspond to entries of a Hadamard matrix of an order equal to a total number of electrodes in the plurality of electrodes.

29. The apparatus of claim 17, wherein the sensing circuitry is configurable to generate, during an integration period, a first composite output signal corresponding to a first voltage reference, a second composite output signal corresponding to a second voltage reference and subtract the second composite output signal from the first composite output signal to remove noise.

30. The apparatus of claim 17, wherein the plurality of outputs of the sensing circuitry are generated by subtracting an output of the second integrator circuit from an output of the first integrator circuit during a plurality of integration periods.

31. The apparatus of claim 25, wherein the demodulation section decodes the self-capacitance measurement from the plurality of outputs of the sensing circuitry based on an inverse of the plurality of values.

32. The apparatus of claim 16, wherein the sensing circuitry is configurable to:

integrate a first input signal comprising signal contributions from one or more of the plurality of electrodes coupled to an input of an integrator circuit during a first portion of an integration period;

integrate a second input signal comprising signal contributions from one or more of the plurality of electrodes coupled to the input of the integrator circuit during a second portion of the integration period; and

generate a composite output signal based on the difference between an output of the integrator circuit during the first portion of the integration period and the output of the integrator circuit during the second portion of the integration period.