COMPUTING SYSTEM AUTOMATICALLY GENERATING A TRANSACTOR

• US 20150339424A1
• Filed: 02/26/2015
• Published: 11/26/2015
• Est. Priority Date: 05/22/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHANG, IN-GWANG
• Granted Patent: US 9,471,736 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A computing system includes a memory device into which a design file for a predetermined intellectual property (IP) and a transactor generating tool are loaded, and a processor configured to execute the transactor generating tool loaded into the memory device. The transactor generating tool executed by the processor extracts port information of the IP from the design file, and generates at least one transactor corresponding to the IP based on the port information.

Claims

1. A computing system, comprising:

a memory device configured to store a design file associated with an intellectual property (IP) and a transactor generating tool; and

a processor configured to execute the transactor generating tool stored in the memory device, wherein the transactor generating tool when executed by the processor extracts port information for the IP from the design file and generates at least one transactor associated with the IP based on the port information.

2. The computing system of claim 1, wherein the port information includes at least one of;

port type information, bit width information, transfer direction information, channel type information and bus type information for at least one port associated with the IP.

3. The computing system of claim 1, wherein the transactor generating tool comprises:

a parsing module that generates a port list for a plurality of ports used by the IP by parsing the design file;

an analyzing module that generates the port information by analyzing the port list; and

a transactor generating module that generates the at least one transactor based on the port information.

4. The computing system of claim 3, wherein the port list generated by the parsing module includes at least one of;

a list of names, bit widths for the plurality of ports, and directions for the plurality of ports.

5. The computing system of claim 4, wherein the analyzing module also groups the plurality of ports into at least one port group according to the list of names included in the port list.

6. The computing system of claim 5, wherein the port information generated by the analyzing module includes at least one of;

type information for ports in the port group, bit width information for the ports in the port group, channel type information corresponding to the port group, bus type information about a bus connected to the port group, and information indicating whether the port group has a master property or a slave property.

7. The computing system of claim 5, wherein the transactor generating module generates at least one transactor for each one of the at least one port group.

8. The computing system of claim 3, wherein the transactor generating module also generates an empty design file for the IP by removing an internal unit of the design file.

9. A computing system, comprising:

a memory device that stores a design file associated with an intellectual property (IP), a transactor generating tool and a bus verification tool; and

a processor configured to execute the transactor generating tool and the bus verification tool stored in the memory device,

wherein the transactor generating tool upon being executed by the processor extracts port information from the design file and automatically generates at least one transactor associated with the IP based on the extracted port information, and

the bus verification tool upon being executed by the processor verifies performance of a bus connected to the IP using the at least one transactor.

10. The computing system of claim 9, wherein the port information includes at least one of;

port type information, bit width information, transfer direction information, channel type information and bus type information for at least one port used by the IP.

11. The computing system of claim 9, wherein the transactor generating tool comprises:

a parsing module that generates a port list for a plurality of ports used by the IP by parsing the design file;

an analyzing module that generates the port information by analyzing the port list; and

a transactor generating module that generates the at least one transactor associated with the IP based on the port information.

12. The computing system of claim 9, wherein the at least one transactor transmits a signal to or receives a signal from the bus in emulation of the IP.

13. The computing system of claim 9, wherein the IP is included in a system-on-chip (SoC).

14. The computing system of claim 9, wherein the bus is a bus of a system-on-chip.

15. The computing system of claim 9, wherein the bus is one of an advanced extensible interface (AXI) bus, an AXI-Lite bus, an AXI coherency extensions (ACE) bus, an ACE-Lite bus, an advanced high performance bus (AHB), an advanced system bus (ASB) or an advanced peripheral bus (APB).

16. A method of verifying the performance of a bus in a system-on-chip including an intellectual property (IP) connected to the bus, the method comprising:

using a transactor generating tool stored in a memory device and executed by a processor to extract port information from a design file associated with the IP, and automatically generate at least one transactor associated with the IP based on the port information.

17. The method of claim 16, wherein executing the transactor generating tool comprises:

using a parsing module to generates a port list for a plurality of ports used by the IP by parsing the design file;

using an analyzing module to generate the port information by analyzing the port list; and

using a transactor generating module to generate the at least one transactor based on the port information.

18. The method of claim 17, wherein the port information includes at least one of;

port type information, bit width information, transfer direction information, channel type information and bus type information for at least one port associated with the IP, and

the port list includes at least one of;

a list of names, bit widths for the plurality of ports, and directions for the plurality of ports.

19. The method of claim 18, further comprising:

using the analyzing module to group the plurality of ports into at least one port group according to the list of names included in the port list.

20. The method of claim 19, wherein the port information includes at least one of;

type information for ports in the port group, bit width information for the ports in the port group, channel type information corresponding to the port group, bus type information about a bus connected to the port group, and information indicating whether the port group has a master property or a slave property.