EXPLOITING PCM WRITE ASYMMETRIES TO ACCELERATE WRITE

• US 20150340091A1
• Filed: 12/20/2013
• Published: 11/26/2015
• Est. Priority Date: 01/04/2013
• Status: Active Grant

• Current Assignee: University of Maine System Board of Trustees
• Original Assignee: University of Maine System Board of Trustees
• Inventors: ZHU, Yifeng, YUE, Jianhui
• Granted Patent: US 9,601,191 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement

Abstract

To improve the write performance of PCM, the disclosed technology, in certain embodiments, provides a new write scheme, referred to herein as two-stage-write, which leverages the speed and power asymmetries of writing a zero bit and a one bit. Writing a data block to PCM is divided into two separated stages, i.e., write-0 stage and write-1 stage. Without violating power constraints, during the write-0 stage, all zero bits in this data block are written to PCM at an accelerated speed; during the write-1 stage, all one bits are written to PCM, with more bits being written concurrently. In certain embodiments, the disclosed technology provides a new coding scheme to improve the speed of the write-1 stage by further increasing the number of bits that can be written to PCM in parallel.

Claims

1. A phase-change memory (PCM) chip comprising a circuit, wherein the circuit comprises:

a buffer, the buffer configured to store one or more bits and to output a buffer signal;

a finite states machine (FSM), the FSM configured to provide an output control, a first write-region control, and a second write-region control, wherein the first and second write-region controls specify which write-region is scheduled;

a first AND gate, the first AND gate configured to receive the output control, the first write-region control, and an inverted buffer signal, wherein the inverted buffer signal is an inversion of the buffer signal output by the buffer;

a second AND gate, wherein the second AND gate is configured to receive the buffer signal, the second write-region control, and an inversion of the output control;

an OR gate, wherein the OR gate is configured to receive an output signal of the first AND gate and an output signal of the second AND gate; and

a switch, the switch configured to provide the buffer signal to a write driver according to an output signal of the OR gate, wherein the write driver writes one or more bits stored in the buffer in the target cache line;

wherein the circuit is configured to schedule writing requests in at least two stages, wherein a first stage comprises writing all bits of zero in a target cache line and a second stage comprises writing all bits of one in the target cache line.

2. The PCM chip of claim 1, wherein the first stage precedes the second stage.

3. The PCM chip of claim 1, comprising a control circuit, wherein the control circuit is configured to:

identify a number of ones in a write unit to be written in the target cache line;

determine that the number of ones in the write unit exceeds half of the write unit size;

based on the determining step, (a) invert all of the bits in the write unit, and (b) store an inversion flag associated with the write unit;

wherein the bits are inverted and the inversion flag is associated prior to the first stage and the second stage.

4. The PCM chip of claim 1, wherein the first stage comprises writing the bits of zero sequentially.

5. The PCM chip of claim 1, wherein the second stage comprises writing one or more bits of one in parallel.

6. The PCM chip of claim 3, wherein the circuit comprises the control circuit.

7. The PCM chip of claim 1, wherein the PCM chip is a single-level-cell (SLC) chip.

8. A phase-change memory (PCM) chip comprising a circuit, the circuit configured to schedule writing requests in at least two stages, wherein a first stage of the at least two stages comprises writing all bits of zero in a target cache line and a second stage of the at least two stages comprises writing all bits of one in the target cache line.

9. The PCM chip of claim 8, wherein the first stage precedes the second stage.

10. The PCM chip of claim 8, comprising a control circuit, wherein the control circuit is configured to:

identify a number of ones in a write unit to be written in the target cache line;

determine if the number of ones in the write unit exceeds half of the write unit size; and

based upon the determining step, (a) invert all of the bits in the write unit, and (b) store an inversion flag associated with the write unit;

wherein the bits are inverted and the inversion flag is associated prior to the first stage and the second stage.

11. The PCM chip of claim 8, wherein the first stage comprises writing the bits of zero sequentially.

12. The PCM chip of claim 8, wherein the second stage comprises writing one or more bits of one in parallel.

13. The PCM chip of claim 10, wherein the circuit comprises the control circuit.

14. The PCM chip of claim 10, wherein the PCM chip is a single-level-cell (SLC) chip.