Deep Trench Isolation Structure and Method for Improved Product Yield

• US 20150340267A1
• Filed: 04/14/2015
• Published: 11/26/2015
• Est. Priority Date: 05/21/2014
• Status: Active Grant

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Inventors: Dornisch, Dieter, Parker, George E., Au, Lawrence L.
• Granted Patent: US 9,997,396 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/735 Lateral transistors

Abstract

A semiconductor structure having a deep trench isolation structure for improved product yield is disclosed. The semiconductor structure includes a deep trench having a filler material therein. The deep trench is adjacent to field oxide regions in a semiconductor substrate. A high density plasma (HDP) oxide layer, substantially free of thermal oxide, is situated over the filler material in the deep trench. The HDP oxide layer has a substantially co-planar top surface with at least one of the field oxide regions. According to the present disclosure, formation of nodules in the deep trench is prevented.

Claims

1. A semiconductor structure comprising:

a deep trench having a filler material therein, said deep trench adjacent to field oxide regions in a semiconductor substrate;

a high density plasma (HDP) oxide layer, substantially free of thermal oxide, situated over said filler material in said deep trench, wherein said HDP oxide layer has a substantially co-planar top surface with at least one of said field oxide regions, thereby preventing nodules in said deep trench.

2. The semiconductor structure of claim 1, wherein said HDP oxide layer is free of thermal oxide.

3. The semiconductor structure of claim 1, wherein said HDP oxide layer, substantially free of thermal oxide, prevents stress under said field oxide regions in said semiconductor substrate.

4. The semiconductor structure of claim 1, wherein said HDP oxide layer, substantially free of thermal oxide, prevents cracking in said semiconductor substrate.

5. The semiconductor structure of claim 1, wherein said filler material comprises polysilicon.

6. The semiconductor structure of claim 1, wherein said HDP oxide layer comprises silicon oxide.

7. The semiconductor structure of claim 1, further comprising an oxide liner in said deep trench.

8. The semiconductor structure of claim 7, wherein said oxide liner comprises a tetraethylorthosilicate (TEOS) liner.

9. The semiconductor structure of claim 7, wherein said oxide liner has a co-planar top surface with said field oxide regions and said HDP oxide layer.

10. The semiconductor structure of claim 1, further comprising a semiconductor device surrounded by said deep trench, wherein said deep trench provides electrical isolation for said semiconductor device.

11. A method comprising:

forming a deep trench adjacent to a field oxide region in a semiconductor substrate;

depositing a filler material into said deep trench;

forming a high density plasma (HDP) oxide layer over said filler material in said deep trench;

planarizing said HDP oxide layer such that said HDP oxide layer has a co-planar top surface with at least one of said field oxide region.

12. The method of claim 11, wherein said HDP oxide layer is formed while substantially avoiding thermal oxidation.

13. The method of claim 11, wherein said HDP oxide layer is formed without causing thermal oxidation.

14. The method of claim 11, wherein said planarizing comprises chemical mechanical polishing.

15. The method of claim 11, wherein said filler material comprises polysilicon.

16. The method of claim 11, wherein said HDP oxide layer comprises silicon oxide.

17. The method of claim 11, further comprising depositing an oxide liner in said deep trench prior to said depositing said filler material.

18. The method of claim 17, wherein said oxide liner comprises a tetraethylorthosilicate (TEOS) liner.

19. The method of claim 17, wherein said oxide liner has a co-planar top surface with said field oxide region and said HDP oxide layer.

20. The method of claim 11, wherein said deep trench surrounds a semiconductor device in said semiconductor substrate to provide electrical isolation for said semiconductor device.