NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20150340316A1
• Filed: 07/31/2015
• Published: 11/26/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Granted Patent: US 10,224,279 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/883 : Oxides or nitrides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A 3D device, including: a first layer including a first memory including a first transistor; and a second layer including a second memory including a second transistor; where the second transistor is self-aligned to the first transistor, and where the first transistor and the second transistor each being a junction-less transistor.

Claims

1. A 3D device, comprising:

a first layer comprising a first memory comprising a first transistor; and

a second layer comprising a second memory comprising a second transistor;

wherein said second transistor is self-aligned to said first transistor, and

wherein said first transistor and said second transistor each being a junction-less transistor.

2. A 3D device according to claim 1,

wherein said first memory is a non-volatile memory comprising a NAND architecture.

3. A 3D device according to claim 1,

wherein said first memory is an RRAM memory comprising a NAND architecture.

4. A 3D device according to claim 1, further comprising:

at least one periphery transistor disposed underneath or above said first memory.

5. A 3D device according to claim 1,

wherein said first memory is a DRAM memory.

6. A 3D device according to claim 1, further comprising:

a vertical control line connecting at least one logic transistor to said first transistor.

7. A 3D device according to claim 1,

wherein said first transistor and said second transistor comprise at least one element that was simultaneously processed following a single lithography step.

8. A 3D device, comprising:

a first layer comprising a first memory comprising a first transistor; and

a second layer comprising a second memory comprising a second transistor;

wherein said second transistor is self-aligned to said first transistor, and

wherein said first transistor source, drain and channel have the same dopant type.

9. A 3D device according to claim 8,

wherein said first memory is a non-volatile memory comprising a NAND architecture.

10. A 3D device according to claim 8,

wherein said first memory is an RRAM memory comprising a NAND architecture.

11. A 3D device according to claim 8, further comprising:

at least one periphery transistor disposed underneath or above said first memory.

12. A 3D device according to claim 8,

wherein said first memory is a DRAM memory.

13. A 3D device according to claim 8, further comprising:

a vertical control line connecting at least one logic transistor to said first transistor.

14. A 3D device according to claim 8,

wherein said first transistor and said second transistor comprise at least one element that was simultaneously processed following a single lithography step.

15. A 3D device, comprising:

a first layer comprising a first memory comprising a first transistor; and

a second layer comprising a second memory comprising a second transistor;

wherein said first transistor and said second transistor comprise at least one element that was simultaneously processed following a single lithography step, and

wherein said first transistor source, drain and channel have the same dopant type.

16. A 3D device according to claim 15,

wherein said first memory is a non-volatile memory comprising a NAND architecture.

17. A 3D device according to claim 15,

wherein said first memory is an RRAM memory comprising a NAND architecture.

18. A 3D device according to claim 15, further comprising:

at least one periphery transistor disposed underneath or above said first memory.

19. A 3D device according to claim 15,

wherein said first memory is a DRAM memory.

20. A 3D device according to claim 15, further comprising:

a vertical control line connecting at least one logic transistor to said first transistor.