SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20150340376A1
• Filed: 02/12/2015
• Published: 11/26/2015
• Est. Priority Date: 05/20/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jang-Hyun You, Jintaek Park, Sunghoi Hur
• Inventors: PARK, Jintaek, HUR, Sunghoi, YOU, Jang-Hyun
• Granted Patent: US 9,299,718 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.

Claims

1. A three-dimensional semiconductor device, comprising:

a substrate including a cell region and a connection region;

gate electrodes stacked on top of each other on the cell region of the substrate, the gate electrodes including a lowermost gate electrode;

a vertical channel structure penetrating the gate electrodes on top of the lowermost gate electrode, the vertical channel structure including a first gate dielectric pattern;

pads extended from the gate electrodes, the pads stacked on top of each other on the connection region of the substrate, the pads including a lowermost pad;

a dummy pillar penetrating at least some of the pads on top of the lowermost pad, the dummy pillar including a second gate dielectric pattern;

a first semiconductor pattern between the vertical channel structure and the substrate, the first gate dielectric pattern of the vertical channel structure on the first semiconductor pattern, the first semiconductor pattern penetrating the lowermost gate electrode; and

a second semiconductor pattern between the dummy pillar and the substrate, the second semiconductor pattern penetrating the lowermost pad, the second gate dielectric pattern of the dummy pillar covering a whole top surface of the second semiconductor pattern.

2. The device of claim 1, wherein the vertical channel structure further includes a first vertical channel pattern and an insulating filling pattern on the first gate dielectric pattern.

3. The device of claim 2, wherein

the first vertical channel pattern is in direct contact with the first semiconductor pattern, and

the first vertical channel pattern is electrically connected to the substrate through the first semiconductor pattern.

6. The device of claim 1, wherein the dummy pillar further includes a second vertical channel pattern on the second gate dielectric pattern.

7. The device of claim 6, wherein

the second gate dielectric pattern defines an inner space of the dummy pillar, and the

second vertical channel pattern completely fills the inner space of the dummy pillar defined by the second gate dielectric pattern.

10. The device of claim 1, wherein the dummy pillar is on or across a boundary between adjacent ones of the pads.

11. The device of claim 1, wherein the vertical channel structure has a circular top surface, and the dummy pillar has an elliptical top surface.

12. The device of claim 11, wherein a short diameter of the elliptical top surface of the dummy pillar is in a range from 50% to 90% of a diameter of the circular top surface of the vertical channel structure.

13. The device of claim 1, wherein the vertical channel structure and the dummy pillar have circular top surfaces.

14. The device of claim 13, wherein a diameter of the circular top surface of the dummy pillar is smaller than or equal to 50% of a diameter of the circular top surface of the vertical channel structure.

15. The device of claim 1, wherein the pads have horizontal lengths decreasing in a direction away from the substrate.

16. The device of claim 1, further comprising:

contact plugs electrically connected to the pads.

4-5. -5. (canceled)

8-9. -9. (canceled)

17. A three-dimensional semiconductor device, comprising:

a substrate including a cell region and a connection region;

gate electrodes stacked on top of each other on the cell region of the substrate, the gate electrodes defining a part of a channel hole that exposes a part of the cell region of the substrate, the gate electrodes being separated from each other in a vertical direction;

pads extended from the gate electrodes, the pads stacked on top of each other on the connection region of the substrate, at least some of the pads defining a part of a dummy hole that exposes a part of the connection region of the substrate;

a first semiconductor pattern on the cell region of the substrate in a lower portion of the channel hole, a top surface of the first semiconductor pattern including a recessed dent; and

a second semiconductor pattern on the connection region of the substrate in a lower portion of the dummy hole, a top surface of the second semiconductor pattern being flat.

18. The device of claim 17, further comprising:

a vertical channel structure on the first semiconductor pattern over the cell region of the substrate.

21. The device of claim 17, further comprising:

a dummy pillar on the second semiconductor pattern over the connection region of the substrate.

19-20. -20. (canceled)

22-30. -30. (canceled)

31. A three-dimensional semiconductor device, comprising:

a substrate including a cell region and a connection region;

a plurality of conductive layers stacked on top of each other on the substrate and spaced apart from each other in a vertical direction, the conductive layers each including a gate electrode portion over the cell region and a pad portion over the connection region;

a first semiconductor pattern on a part of the cell region, the first semiconductor pattern extending vertically through the gate electrode portion of a lowermost conductive layer among the plurality of conductive layers;

a first vertical channel pattern extending vertically through the gate electrode portions of the conductive layers over the lowermost conductive layer, the first vertical channel pattern electrically connected to the first semiconductor pattern;

a second semiconductor pattern on a part of the connection region and extending vertically through the pad portion of the lowermost conductive layer; and

a dummy gate dielectric pattern extending vertically through the pad portions of some of the conductive layers over the lowermost conductive layer, the dummy gate dielectric pattern covering a whole top surface of the second semiconductor pattern.

32. The device of claim 31, further comprising:

a cell region gate dielectric pattern between the first vertical channel pattern and the gate electrode portions of the conductive layers on the lowermost conductive layer, wherein the cell region gate dielectric pattern is on top of the first semiconductor pattern.

33. The device of claim 32, wherein

the cell region gate dielectric pattern and the first vertical channel pattern define a vertical channel structure,

the vertical channel structure has a circular top surface,

an outer periphery of the dummy gate dielectric pattern has an elliptical top surface.

34. The device of claim 33, wherein a short diameter of the elliptical top surface of the outer periphery of the dummy gate dielectric pattern is in a range from 50% to 90% of a diameter of the circular top surface of the vertical channel structure.

35. The device of claim 31, wherein the pad portions of the conductive layers define a staircase structure over the connection region.