PACKAGE OF FINGER PRINT SENSOR AND FABRICATING METHOD THEREOF

• US 20150340399A1
• Filed: 08/04/2015
• Published: 11/26/2015
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Jin Young, Kim, Yoon Joo, Kim, Sung Kyu, Park, No Sun, Lee, Seung Jae, Cha, Se Woong, Yoon, Ju Hoon
• Granted Patent: US 9,431,447 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06V 40/12 Fingerprints or palmprints
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14678 Contact-type imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect

Abstract

Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Claims

1-14. -14. (canceled)

15. A semiconductor device comprising

a semiconductor die comprising a first surface, a second surface opposite the first surface, and side surfaces connecting the first and second surfaces, where the first surface comprises an image sensor and a plurality of bond pads;

an encapsulant surrounding the side surfaces, but not the first and second surfaces, of the semiconductor die;

a first lower passivation layer covering the first surface of the semiconductor die and comprising openings that expose the bond pads;

first redistribution layers (RDLs) electrically connected to the bond pads exposed through the first lower passivation layer;

a first upper passivation layer covering the second surface of the semiconductor die;

a plurality of vias electrically connected to the first RDLs at a first end of the vias and passing through the encapsulant;

second RDLs electrically connected to a second end of the vias and formed on the first upper passivation layer;

a second upper passivation layer exposing first portions of the second RDLs and covering second portions of the second RDLs and at least a portion of the encapsulant; and

electrical connection structures coupled to the exposed first portions of the second RDLs.

16. The semiconductor device of claim 15, wherein the first RDLs extend outside a footprint of the semiconductor die.

17. The semiconductor device of claim 15, wherein the first lower passivation layer and the encapsulant are made of a same material.

18. The semiconductor device of claim 15, comprising a second lower passivation layer covering the first lower passivation layer and the first RDLs.

19. The semiconductor device of claim 18, wherein the first lower passivation layer, the second lower passivation layer, and the encapsulant are made of a same material.

20. The semiconductor device of claim 15, wherein at least one of the first RDLs comprises a ground pattern for protecting the image sensor against electrostatic discharge.

21. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises an image sensor and a bond pad;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connecting the bond pad to a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via; and

an electrical interconnection structure coupled to the second conductive layer.

22. The semiconductor device of claim 21, comprising a first dielectric layer between the first conductive layer and the first die surface and between the first conductive layer and the first encapsulant surface, wherein the first dielectric layer comprises a first aperture through which the first conductive layer and the bond pad are connected and a second aperture through which the first conductive layer and the first end of the conductive via are connected.

23. The semiconductor device of claim 22, wherein the encapsulant and the first dielectric layer are made of a same material.

24. The semiconductor device of claim 22, comprising a second dielectric layer between the second conductive layer and the second die surface and between the second conductive layer and the second encapsulant surface, wherein the second dielectric layer comprises a third aperture through which the second conductive layer and the second end of the conductive via are connected.

25. The semiconductor device of claim 21, wherein the electrical interconnection structure is positioned directly over the second die surface.

26. The semiconductor device of claim 21, wherein the first conductive layer comprises an electrostatic discharge protection pattern.

27. The semiconductor device of claim 21, wherein the electrical interconnection structure comprises one of:

a land of a land grid array or a conductive ball.

28. The semiconductor device of claim 21, wherein the semiconductor device comprises a complete packaged finger print sensor without a printed wire board substrate.

29. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises an image sensor and a plurality of bond pads;

an encapsulant surrounding at least the side die surfaces;

a first dielectric layer covering the first die surface and comprising openings that expose the bond pads;

first conductive layers electrically connected to the bond pads exposed through the first dielectric layer;

a plurality of vias electrically connected to the first conductive layers at a first end of the vias and passing through the encapsulant;

second conductive layers electrically connected to a second end of the vias;

a second dielectric layer exposing first portions of the second conductive layers and covering second portions of the second conductive layers and at least a portion of the encapsulant; and

electrical connection structures coupled to the exposed first portions of the second conductive layers.

30. The semiconductor device of claim 29, wherein the second die surface is exposed from the encapsulant.

31. The semiconductor device of claim 29, wherein the second die surface and a second encapsulant surface of the encapsulant are coplanar, and the second dielectric layer covers the second die surface and the second encapsulant surface.

32. The semiconductor device of claim 29, wherein at least one of the electrical connection structures is positioned directly over the second die surface.

33. The semiconductor device of claim 29, comprising a third dielectric layer between the second conductive layers and the second die surface and between the second conductive layers and the encapsulant.

34. The semiconductor device of claim 29, wherein the first RDL comprises an electrostatic discharge protection pattern.