METHOD OF MANUFACTURING A MICRO-FABRICATED WAFER LEVEL INTEGRATED INDUCTOR OR TRANSFORMER FOR HIGH FREQUENCY SWITCH MODE POWER SUPPLIES

• US 20150340422A1
• Filed: 05/23/2014
• Published: 11/26/2015
• Est. Priority Date: 05/23/2014
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lee, Dok Won, French, William D., Papou, Andrei
• Application Number:
  US14/286,562
• Publication Number:
  US 20150340422A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03622 using masks
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1705 Shape
• CPC Class Codes: H01L 2224/30505 Layer connectors having different materials
• CPC Class Codes: H01L 2224/80031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/80862 Heat curing
• CPC Class Codes: H01L 2225/1011 the containers being in a stacked arrangement
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/06 : Polymers
• CPC Class Codes: H01L 2924/364 : Polymers

Abstract

A method of manufacturing an inductor on a wafer level process that can operate at 20 MHz with good efficiency and a high inductance density is disclosed, wherein the inductor design allows high frequency operation, low RDSON values and high efficiency.

Claims

1. An integrated magnetic device, comprising:

a silicon wafer substrate, an active region thereupon further comprising transistors, diodes, capacitors and resistors coupled by a conductive interconnect layer to form an active circuit, wherein the active region touches the top surface of the silicon wafer substrate and includes a first plurality of bond contacts, wherein the conductive interconnect layer is comprised of multiple layers of conductive material with insulating layer therebetween, the multiple layers of conductive material coupled together by a first plurality of vias piercing their associated insulating layer, wherein the top of the conductive interconnect layer is an insulating layer, having openings to expose a first plurality of bond contacts;

a Silicon Nitride layer overlaying and touching the insulating layer, also having openings to expose the first plurality of bond contacts;

a first layer of polymer deposited on top of the Silicon Nitride layer including a first plurality openings extending from the top of the first layer of polymer down to the first plurality of bond contacts;

a first layer high conductance material, deposited on the top surface of the first layer of polymer, tilling the first plurality of openings in the first polymer layer, forming the second plurality of vias, thereby coupling the first layer of high conductance material to the first plurality of bond contacts, wherein the first layer of high conductance material is configured to form a plurality of lower coil members and also includes a second plurality of bond contacts;

a second layer of polymer, touching the first layer of polymer and the first layer of high conductance material, wherein the top surface of the second layer of polymer is planar, the second layer of polymer include a second plurality of openings extending from the top surface of the second layer of polymer down to the second plurality of bond contacts, wherein the second plurality of openings in the second layer of polymer are filled with a third plurality of vias;

multiple layers of alternating magnetic film material and insulating material deposited and defined on the top surface of second layer of polymer, wherein the multiple layers of alternating magnetic film material and insulating material, as defined, do not touch the third plurality of vias exposed on the top surface of the second layer of polymer;

a third layer of polymer is deposited touching the second layer of polymer and the top of the multiple layers of alternating magnetic material and insulating material, the third layer of polymer includes a third plurality of openings extending from the top surface of the third layer of polymer down to the top surfaces of the third plurality of vias;

a second layer high conductance material is deposited on the top surface of the third layer of polymer, wherein the second layer of high conductance material fills the third plurality of openings in the third polymer layer, forming a fourth plurality of vias, thereby coupling the second layer of high conductance material to the first plurality of bond contacts, the third layer of high conductance material is configured to form a plurality of upper coil members and also includes a third plurality of bond contacts; and

a fourth layer of polymer is deposited touching the third layer of polymer and the top of the second layer high conductance material, wherein the fourth layer of polymer includes openings extending from the top surface of the fourth layer of polymer down to the top surfaces second layer high conductance material, the openings in the fourth layer of polymer are filled with solder balls, wherein the solder balls provide connection to outside circuitry.

2. The integrated magnetic device of claim 1, wherein the first layer of polymer is configured to act as a stress relief layer between an inductor and the silicon wafer, wherein the thickness of the first layer of polymer is between 5 μ

m-15 μ

m, the first layer of polymer is chosen from the group of polymers SU8 or PI-2622.

3. The integrated magnetic device of claim 1, wherein he second layer of polymer is chosen from the group of polymers SU8 3000 or PI-2622.

5. The integrated magnetic device of claim 1, wherein the laminated magnetic core total thickness is between 5-15 μ

m.

6. The integrated magnetic device of claim 1, wherein the first and second layers of high conductance material are comprised of copper with a thickness of 20 μ

m.

4. The integrated magnetic device of claim I, wherein each magnetic film layer has a thickness that ranges from 0.1 μ

m to 3 μ

m with a 10 nm AlN dielectric in between, the composition of the magnetic film layers are selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN.

7. A method of forming an integrated magnetic device, comprising:

providing a conventionally formed integrated circuit wafer wherein bond contacts of each of the integrated circuits are exposed through openings in the insulating layer at the top of the conductive interconnect layer;

depositing and defining a layer of silicon nitride over the wafer, wherein the silicon nitride layer touches the insulating layer at the top of the conductive interconnect layer and exposes the bond pads exposed through the openings in the insulating layer at the top of the conductive interconnect layer, by using a pattern and etch process, the bond contacts are exposed through openings in the silicon nitride layer;

spinning and patterning a first layer of polymer onto the wafer chosen from group of polymers SU8 or PI-2622;

sputtering a first seed layer of Ti/Cu on the top surface of the first layer of polymer;

spinning and patterning a photoresist layer on the first seed layer using standard photo lithography processes;

electroplating a first layer of high conductance material on the surface of the photoresist and into the open areas defined by the photoresist, touching the first seed layer and defining a plurality of lower coil members which include a second plurality of contacts, filling the first plurality of openings in the first polymer layer, thereby coupling the first layer of high conductance material to the first plurality of bond contacts;

stripping the photoresist layer, using standard photoresist stripping methods and dry etching the exposed first seed layer;

spinning a second layer of polymer onto the wafer and baking it to cure the polymer layer;

depositing a patterned hard mask on the wafer touching the top surface of the second polymer, wherein a second plurality of openings are etched into the second polymer layer extending from the top surface of the second polymer layer down to the second plurality of contacts;

removing the hard mask;

sputtering a second seed layer of Ti/Cu on the top surface of the first layer of polymer;

spinning and patterning a photoresist layer on the second seed layer using standard photo lithography processes;

electroplating a layer of high conductance material into the open areas defined by the photoresist, touching the second seed layer and defining a first plurality of vias, thereby coupling the first plurality of vias to the first plurality of bond contacts;

stripping the photoresist layer, using standard photoresist stripping methods and dry etching the exposed second seed layer;

sputtering a layer of titanium on the top surface of the second layer of polymer, touching the second layer of polymer and the tops of the first plurality of vias;

depositing a laminated magnetic core comprised of multiple layers of alternating magnetic film material and insulating material using a Veeco Nexus PVDi Tool, in a magnetic field, on the top surface of the layer of titanium, wherein the multiple layers of alternating magnetic material and insulating material are defined to not touch the first plurality of vias exposed on the top surface of the second layer of polymer;

patterning and etching of the multiple layers of alternating magnetic material and insulating material and the titanium layer, using standard photo resist processes, the photoresist is then stripped using standard techniques;

spinning a third layer of polymer onto the wafer and baking it to cure the polymer layer;

depositing a patterned hard mask on the wafer touching the top surface of the third polymer layer, wherein a third plurality of openings are etched into the third polymer layer extending from the top surface of the third polymer layer down to the first plurality vias;

removing the hard mask;

sputtering a third seed layer of Ti/Cu on the top surface of the third layer of polymer;

spinning and patterning a photoresist layer on the third seed layer using standard photo lithography processes;

electroplating a second layer of high conductance material on the surface of the photoresist and into the open areas defined by the photoresist, touching the third seed layer and defining a plurality of upper coil members which include a second plurality of contacts, filling the third plurality of openings in the third polymer layer, thereby coupling the second layer of high conductance material to the first plurality of bond contacts;

stripping the photoresist layer, using standard photoresist stripping methods and dry etching the exposed first seed layer;

depositing a fourth layer of polymer, touching the third layer of polymer and the second layer of high conductance material, the fourth layer of polymer includes openings extending from the top surface of the fourth layer of polymer down through the fourth layer of polymer to the second layer of high conductance material;

subjecting the magnetic layers to a second anneal (300-500C) in the presence of a magnetic field (0.1-1T), wherein the second anneal further defines the easy/hard axes; and

forming solder bumps in the openings formed in the fourth layer of polymer, touching the second layer of high conductance material.

8. The method of forming an integrated magnetic device of claim 7, wherein the second layer of polymer is chosen from the group of polymers SU8 3000 or PI-2622, wherein if PI-2622 is chosen, a CMP process is used to planarize the surface, also wherein if SU8 3000 is used instead of PI-2622 for the second Polymer layer, CMP is not required because SU8 3000 is largely self-planarizing to the required tolerance.

9. The method of forming an integrated magnetic device of claim 7, wherein each magnetic film layer is sputtered, with thickness ranges from 0.1 μ

m to 3 μ

m with a 10 nm AlN dielectric therebetween, wherein the total laminated magnetic thickness is between 5-15 μ

m, the sputtering is accomplished in the presence of a magnetic field to determine the easy axis of the magnetic material, wherein the orientation is such that the B-field in the multiple layers of alternating magnetic material and insulating material is in the direction of the hard axis.

10. The method of forming an integrated magnetic device of claim 7, wherein the magnetic film layers can he selected from the group of Ni80Fe20, Co90Ta5Zr5 or FeAlN.

11. The method of forming an integrated magnetic device of claim 7, wherein the magnetic film layers are subjected to an anneal of 300-500°

C., in the presence of a magnetic field after sputtering, further defining the easy/hard axes.

12. The method of forming an integrated magnetic device of claim 7, wherein the first and second layers of high conductance material are comprised of copper with a thickness of 20 μ

m.

13. The method of forming an integrated magnetic device of claim 7, wherein the first layer of polymer is configured to act as a stress relief layer between an inductor and the silicon wafer, wherein the thickness of the first layer of polymer is between 5 μ

m-15 μ

m, the first layer of polymer is chosen from the group of polymers SU8 or PI-2622.

14. The method of thrilling an integrated magnetic device of claim 7, wherein the first layer of polymer is PI-2622, and is then baked after spinning to cure the polymer layer, depositing a patterned hard mask on the wafer touching the top surface of the first polymer layer, wherein a first plurality of openings are etched into the first polymer layer extending from the top surface of the first polymer layer down to the plurality of bond contacts, removing the hard mask.

15. The method of forming an integrated magnetic device of claim 7, wherein the first layer of polymer is SU8, is then soft baked after spinning, depositing and patterning a photoresist layer on the wafer touching the top surface of the first polymer layer, wherein an exposure by a light source takes place, following the exposure, a post exposure bake is performed, wherein the photoresist and the unexposed SU8 is then developed off, wherein the SU8 is then hard baked after developing, the SU8 exposed to the light source will remain on the wafer after the developing process.