LOW POWER MULTI-STACKED POWER AMPLIFIER

• US 20150340992A1
• Filed: 05/23/2014
• Published: 11/26/2015
• Est. Priority Date: 05/23/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Korol, Victor, Liao, Shu-Hsien
• Granted Patent: US 9,419,560 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0272 by using a signal derived from the output signal
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only

Abstract

An apparatus includes a plurality of stacked transistors in a multi-stacked power amplifier. At least one transistor of the plurality of stacked transistors is configured to operate in a first mode and in a second mode. The at least one transistor of the plurality of stacked transistors is configured to be biased by a low power biasing network to operate in the first mode.

Claims

1. An apparatus comprising:

a plurality of stacked transistors in a multi-stacked power amplifier, at least one transistor of the plurality of stacked transistors configured to operate in a first mode and in a second mode; and

the at least one transistor of the plurality of stacked transistors configured to be biased by a low power biasing network to operate in the first mode.

2. The apparatus of claim 1, wherein the at least one transistor of the plurality of stacked transistors is configured to be biased by a high power biasing network to operate in the second mode.

3. The apparatus of claim 2, further comprising a first gate biasing network coupled to a gate of a first transistor of the plurality of stacked transistors.

4. The apparatus of claim 3, further comprising:

a first switch configured to couple a gate of a second transistor of the plurality of stacked transistors to the low power biasing network; and

a second switch configured to couple a gate of a third transistor of the plurality of stacked transistors to the low power biasing network.

5. The apparatus of claim 4, further comprising:

a third switch configured to couple the gate of the second transistor of the plurality of stacked transistors to the high power biasing network; and

a fourth switch configured to couple the gate of the third transistor of the plurality of stacked transistors to the high power biasing network.

6. The apparatus of claim 2, wherein the high power biasing network comprises a voltage divider circuit.

7. The apparatus of claim 1, further comprising an input matching network coupled to a gate of a first transistor of the plurality of stacked transistors.

8. The apparatus of claim 1, further comprising an output matching network coupled to an output of a transistor of the plurality of stacked transistors.

9. The apparatus of claim 1, wherein the first mode corresponds to a linear region of operation, and wherein the second mode corresponds to a saturation region of operation.

10. An apparatus comprising:

means for amplifying an input signal in a multi-stacked power amplifier, the means for amplifying the input signal including a plurality of stacked transistors, at least one of the transistor of the plurality of stacked transistors configured to operate in a first mode and in a second mode; and

first means for generating a bias voltage configured to bias the at least one transistor of the plurality of stacked transistors to operate in the first mode.

11. The apparatus of claim 10, further comprising second means for generating a bias voltage configured to bias the at least one transistor in the plurality of stacked transistors to operate in the second mode.

12. The apparatus of claim 10, further comprising third means for generating a bias voltage coupled to a gate of a first transistor of the plurality of stacked transistors.

13. The apparatus of claim 11, further comprising:

first means for switching configured to couple a gate of a second transistor of the plurality of stacked transistors to the first means for generating the bias voltage; and

second means for switching configured to couple a gate of a third transistor of the plurality of stacked transistors to the first means for generating the bias voltage.

14. The apparatus of claim 13, further comprising:

third means for switching configured to couple the gate of the second transistor of the plurality of stacked transistors to the second means for generating the bias voltage; and

fourth means for switching configured to couple the gate of the third transistor of the plurality of stacked transistors to the second means for generating the bias voltage.

15. The apparatus of claim 11, wherein the second means for generating the bias voltage comprises a voltage divider circuit.

16. The apparatus of claim 10, wherein the first mode corresponds to a linear region of operation, and wherein the second mode corresponds to a saturation region of operation.

17. A method comprising:

selectively coupling a gate of a transistor of a plurality of stacked transistors to a low power biasing network to operate the transistor in a first mode during a low power mode of a multi-stacked power amplifier; and

selectively coupling the gate of the transistor to a high power biasing network to operate the transistor in a second mode during a high-power mode of the multi-stacked power amplifier.

18. The method of claim 17, wherein the first mode corresponds to a linear region of operation.

19. The method of claim 17, wherein the second mode corresponds to a saturation region of operation.

20. The method of claim 17, wherein the transistor is an n-type metal oxide semiconductor (NMOS) transistor.