Methods for Mitigating System Interrupts for an Electronic Device

• US 20150347328A1
• Filed: 09/02/2014
• Published: 12/03/2015
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Dominguez, Charles F., Kapur, Ashima, Kattel, Kiran
• Granted Patent: US 10,838,893 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 2209/548 Queue
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

An electronic device may include an applications processor that communicates with a peripheral input-output (I/O) device using a coprocessor. The applications processor may include a first interprocessor communications (IPC) module, whereas the coprocessor may include a second IPC module for interfacing with the first IPC module. The first IPC module may forward a group of transactions to a submission queue and may ring a submission doorbell interrupt to signal that work items are pending in the submission queue. In response, the second IPC module may dequeue the work items from the submission queue and process these items at the I/O device. The second IPC module may provide a group of completed transactions to a completion queue and may ring a completion doorbell interrupt to signal that items are pending in the completion queue. Thereafter, the completed items are forwarded to other parts of the applications processor for processing.

Claims

1. A method for operating an electronic device that includes a main processor and a coprocessor for interfacing with an input-output device, comprising:

with the main processor, passing a group of submitted transactions into a submission queue; and

in response to receiving the group of submitted transactions in the submission queue, using the main processor to assert a submission interrupt signal to indicate to the coprocessor that the group of submitted transactions is pending in the submission queue.

2. The method defined in claim 1, further comprising:

with the coprocessor, passing a group of completed transactions into a completion queue; and

in response to receiving the group of completed transactions in the completion queue, using the coprocessor to assert a completion interrupt signal to indicate to the main processor that the group of completed transactions is pending in the completion queue.

3. The method defined in claim 2, further comprising:

monitoring a fill level of the submission queue using a coprocessor communications management module at the main processor, wherein the coprocessor communications management module is also used to assert the submission interrupt signal.

4. The method defined in claim 3, further comprising:

monitoring a fill level of the completion queue using a main processor communications management module at the coprocessor, wherein the main processor communications module is also used to assert the completion interrupt signal.

5. The method defined in claim 1, further comprising:

in response to receiving the asserted submission interrupt signal, using the coprocessor to obtain the group of submitted transactions from the submission queue; and

while the coprocessor is processing the group of submitted transactions obtained from the submission queue, temporarily disabling use of the submission interrupt signal to avoid interrupts to the coprocessor.

6. The method defined in claim 2, further comprising:

in response to receiving the asserted completion interrupt signal, using the main processor to obtain the group of completed transactions from the completion queue; and

while the main processor is processing the group of completed transactions obtained from the completion queue, temporarily disabling use of the completion interrupt signal to avoid interrupts to the main processor.

7. The method defined in claim 1, wherein passing the group of submitted transactions into the submission queue comprises forwarding a complete burst of continuous transactions to the submission queue.

8. The method defined in claim 4, further comprising:

with the main processor communications management module, sending an alert to the main processor when the fill level of the submission queue falls below a predetermined threshold.

9. The method defined in claim 3, further comprising:

with the coprocessor communications management module, sending an alert to the coprocessor when the fill level of the completion queue falls below a predetermined threshold.

10. The method defined in claim 2, wherein the electronic device also includes a system memory that is accessible to both the main processor and the coprocessor, the method further comprising:

storing contents of the submission queue and the completion queue in the system memory.

11. A method of operating an input-output processor (IOP) that includes a transactions management module and a driver module, comprising:

with the transactions management module, receiving a submission interrupt signal;

in response to receiving the submission interrupt signal, dequeuing submitted work items from a submission queue; and

using the transactions management module to send a command to the driver module for directing the driver module to initiate communications with peripheral input-output hardware that is being managed by the input-output processor.

12. The method defined in claim 11, further comprising:

with the driver module, receiving at least one interrupt from the peripheral input-output hardware.

13. The method defined in claim 11, further comprising:

when at least one of the submitted work items is completed, enqueuing the completed work item to a completion queue using the transactions management module.

14. The method defined in claim 13, wherein the completed work item has a transaction latency requirement, the method further comprising:

with the transactions management module, configuring a timer to expire based on the transaction latency requirement of the completed work item and a current deadline associated with the timer.

15. The method defined in claim 14, further comprising:

when the timer expires, using the transactions management module to enqueue the completed work item and other completed work items into a completion queue and to output a completion interrupt signal to indicate to another processor that the completed work items are pending in the completion queue.

16. An electronic device, comprising:

an applications processor for running user applications on the electronic device;

an input-output device; and

an input-output subsystem that is coupled between the applications processor and the input-output device, wherein the input-output subsystem includes a coprocessor for actively managing communications with the input-output device.

17. The electronic device defined in claim 16, wherein the input-output device comprises a Secure Digital Input-Output (SDIO) device configured to support a wireless communications protocol.

18. The electronic device defined in claim 16, wherein the input-output subsystem receives a subsystem clock, and wherein the subsystem clock is ungated only when the input-output subsystem is actively processing transactions generated by the applications processor.

19. The electronic device defined in claim 16, wherein the input-output subsystem further includes an input-output host controller, wherein an input-output bus is interposed between the input-output host controller and the input-output device, and wherein the input-output bus is controlled by a bus clock signal that is ungated only when the input-output subsystem is actively communicating with the input-output host controller.

20. The electronic device defined in claim 19, wherein the applications processor is configured to output a submission interrupt doorbell to the input-output subsystem, wherein the input-output host controller is controlled by a host controller clock signal, and wherein the host controller clock signal is ungated after the input-output subsystem receives the submission interrupt doorbell and is gated before the input-output subsystem outputs a completion interrupt doorbell to the applications processor.