ELECTRONIC COMPARISON SYSTEMS

• US 20150347896A1
• Filed: 05/27/2014
• Published: 12/03/2015
• Est. Priority Date: 05/27/2014
• Status: Active Grant

• Current Assignee: Purdue Research Foundation (The Trustees of Purdue University (d/b/a Purdue University))
• Original Assignee: Purdue Research Foundation (The Trustees of Purdue University (d/b/a Purdue University))
• Inventors: Roy, Kaushik, Sharad, Mrigank
• Granted Patent: US 9,489,618 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 15/02 using magnetic elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.

Claims

1. An electronic comparison system, comprising:

a) a plurality of input stages, each configured to successively provide bits of a respective code word, starting with a most-significant bit thereof;

b) a plurality of one-shots connected to respective ones of the input stages to successively receive the bits of the respective code words, wherein each one-shot is configured to successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then to provide a second, different bit value;

c) an enable circuit connected to the outputs of the one-shots and configured to provide the enable signal if at least one of the one-shots is providing the first bit value.

2. The system according to claim 1, wherein the enable circuit includes a node selectively carrying the enable signal, a precharge circuit configured to precharge the node to a signal level different from the enable signal, and a modification circuit configured to provide the enable signal on the node in response to the first bit value from at least one of the one-shots.

3. The system according to claim 2, wherein the precharge circuit includes a pullup, the discharge circuit includes respective selective pulldowns controlled by the outputs of respective ones of the one-shots, the enable signal corresponds to a low signal level of the node, and the signal level different from the enable signal corresponds to a high signal level of the node.

4. The system according to claim 1, wherein the non-preferred value is 0.

5. The system according to claim 4, wherein the first bit value is 1 and the second, different bit value is 0.

6. The system according to claim 1, wherein each of the one-shots includes an AND gate and first and second D flip-flops (DFFs) enabled by the enable signal, the output of the first DFF and the input of the first DFF are connected as the inputs of the AND gate, and the output of the AND gate is connected to the input of the second DFF.

7. The system according to claim 6, further including a gate configured to force the input of the first DFF to the non-preferred value if the output of the second DFF is the second, different bit value and the enable signal is provided.

8. The system according to claim 1, further comprising a controller programmed to sequence through a selected number of bits and a plurality of successive-approximation analog-to-digital converters (ADCs), wherein the each input stage successively receives the bits from a respective one of the ADCs and each ADC comprises:

a) an input terminal;

b) a register connected to the respective input stage to successively provide the bits;

c) a programmable reference that provides a reference electrical signal in response to the value in the register; and

d) a comparator configured to compare an electrical signal at the input terminal to the reference electrical signal and adjust a bit in the register indicated by the controller, wherein the comparator includes a domain-wall neuron connected to the input terminal and the programmable reference and a CMOS latch configured to compare an output of the domain-wall neuron with a selected threshold and store a bit value according to the result of the comparison.

9. The system according to claim 8, wherein the programmable reference includes a binary-weighted transistor digital-to-analog converter (DAC) responsive to the value in the register to provide the reference electrical signal.

10. The system according to claim 8, further including:

a) a crossbar array having a plurality of row electrodes, a plurality of column electrodes, and a plurality of resistive memory elements, each memory element directly connected to one of the row electrodes and one of the column electrodes; and

b) a signal source configured to apply a plurality of test electrical signals to respective ones of the row electrodes;

c) wherein the column electrodes are electrically connected to the input terminals of the respective ADCs.

11. The system according to claim 10, further including a writing circuit configured to store selected values in the resistive memory elements.

12. The system according to claim 11, further including a controller configured to automatically:

a) receive an input vector and a plurality of test vectors;

b) operate the writing circuit to store values from each of the test vectors in the resistive memory elements directly connected to a respective one of the column electrodes;

c) operate the signal source to apply the test electrical signals corresponding to the input vector;

d) determine which one(s) of the test vectors satisfy a selected criterion with respect to the input vector using the outputs of the one-shots.

13. A neural network system, comprising:

a) a crossbar array having a plurality of row electrodes, a plurality of column electrodes, and a plurality of resistive memory elements, each memory element directly connected to one of the row electrodes and one of the column electrodes;

b) a writing circuit configured to store selected weights in the resistive memory elements; and

c) a signal source configured to apply a plurality of test electrical signals to respective ones of the row electrodes;

d) a reference source configured to provide one or more reference electrical signal(s); and

e) a plurality of comparators, each configured to compare an electrical signal on a respective one of the column electrodes to a corresponding one of the reference electrical signal(s), wherein each comparator includes;

i) a domain-wall neuron connected to the respective column electrode and the reference source; and

ii) a CMOS latch configured to compare an output of the domain-wall neuron with a selected threshold and store a bit value according to the result of the comparison.

14. The system according to claim 13, further including a processor configured to receive the respective stored bit values of the comparators, determine updated weights using the selected weights, the test electrical signals, and the received bit values, and cause the writing circuit to store the updated weights in the resistive memory elements.

15. The system according to claim 13, wherein:

a) the reference source includes;

i) a controller programmed to sequence through a selected number of bits, starting with a most-significant bit of the selected number of bits; and

ii) a plurality of reference circuits, each configured to provide one of the reference electrical signal(s) to a respective one of the comparators;

b) each reference circuit includes;

i) a register configured to hold respective values for the selected number of bits; and

ii) a signal generator that provides the respective one of the reference electrical signals in response to the values in the register; and

c) the controller is configured to successively update the bits of each of the registers in the sequence according to the stored bit value in the respective one of the comparators.

16. The system according to claim 15, wherein each signal generator includes a binary-weighted transistor digital-to-analog converter (DAC) responsive to the values in the respective register to provide the respective one of the reference electrical signals.

17. The system according to claim 15, further including a processor configured to receive the respective bit values in the registers, determine updated weights using the selected weights, the test electrical signals, and the received bit values, and cause the writing circuit to store the updated weights in the resistive memory elements.