ELECTRONIC COMPARISON SYSTEMS
First Claim
1. An electronic comparison system, comprising:
- a) a plurality of input stages, each configured to successively provide bits of a respective code word, starting with a most-significant bit thereof;
b) a plurality of one-shots connected to respective ones of the input stages to successively receive the bits of the respective code words, wherein each one-shot is configured to successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then to provide a second, different bit value;
c) an enable circuit connected to the outputs of the one-shots and configured to provide the enable signal if at least one of the one-shots is providing the first bit value.
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Abstract
An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.
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Citations
17 Claims
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1. An electronic comparison system, comprising:
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a) a plurality of input stages, each configured to successively provide bits of a respective code word, starting with a most-significant bit thereof; b) a plurality of one-shots connected to respective ones of the input stages to successively receive the bits of the respective code words, wherein each one-shot is configured to successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then to provide a second, different bit value; c) an enable circuit connected to the outputs of the one-shots and configured to provide the enable signal if at least one of the one-shots is providing the first bit value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A neural network system, comprising:
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a) a crossbar array having a plurality of row electrodes, a plurality of column electrodes, and a plurality of resistive memory elements, each memory element directly connected to one of the row electrodes and one of the column electrodes; b) a writing circuit configured to store selected weights in the resistive memory elements; and c) a signal source configured to apply a plurality of test electrical signals to respective ones of the row electrodes; d) a reference source configured to provide one or more reference electrical signal(s); and e) a plurality of comparators, each configured to compare an electrical signal on a respective one of the column electrodes to a corresponding one of the reference electrical signal(s), wherein each comparator includes; i) a domain-wall neuron connected to the respective column electrode and the reference source; and ii) a CMOS latch configured to compare an output of the domain-wall neuron with a selected threshold and store a bit value according to the result of the comparison. - View Dependent Claims (14, 15, 16, 17)
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Specification