EXPANSION METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

• US 20150348821A1
• Filed: 12/26/2013
• Published: 12/03/2015
• Est. Priority Date: 12/26/2012
• Status: Active Grant

• Current Assignee: Resonac Corp. (Resonac Holdings Corp.)
• Original Assignee: Hitachi Chemical Company Limited (Resonac Holdings Corp.)
• Inventors: IWANAGA, Yukihiro, SUZUMURA, Kouji, SAKUTA, Tatsuya
• Granted Patent: US 10,008,405 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/68 for positioning, orientation or alignment
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/27 Manufacturing methods
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83862 Heat curing
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.

Claims

1. An expansion method comprising:

a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape,

a step (IIA) of expanding the dicing tape with the laminate in a cooled state,

a step (IIB) of loosening the expanded dicing tape, and

a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

2. An expansion method according to claim 1 comprising:

a step (Ia) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film, a dicing tape and a frame,

a step (Ib) of supplying the laminate to a height-adjustable expansion stage of an expansion apparatus comprising the expansion stage and a fastening member capable of fastening the frame,

a step (Ic) of fastening the frame using the fastening member,

a step (IIa) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state,

a step (IIb) of lowering the raised expansion stage and loosening the expanded dicing tape, and

a step (IIc) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

3. An expansion method according to claim 1 comprising:

a step (Ia′

) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film, a dicing tape and a frame,

a step (Ib′

) of supplying the laminate to a height-adjustable expansion ring of an expansion apparatus comprising the expansion ring and a fastening member capable of fastening the frame,

a step (Ic′

) of fastening the frame using the fastening member,

a step (IIa′

) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state,

a step (IIb′

) of lowering the raised expansion ring and loosening the expanded dicing tape, and

a step (IIc′

) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

4. The expansion method according to claim 1, wherein expansion of the dicing tape is performed by applying an external force to the dicing tape, and an external force applied to the dicing tape in the step (IIC) is greater than an external force applied to the dicing tape in the step (IIA).

5. A method for manufacturing a semiconductor device comprising:

a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape,

a step (II) of expanding the dicing tape, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips,

a step (III) of picking up a chip from the dicing tape,

and a step (IV) of die bonding the chip to an adherend, wherein

the step (I) and the step (II) are performed using the expansion method according to claim 1.

6. A semiconductor device having an adherend, and a chip bonded to the adherend, wherein the semiconductor device is manufactured using the method for manufacturing a semiconductor device according to claim 5.