SEMICONDUCTOR DEVICE WITH VOIDS WITHIN SILICON-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

• US 20150348825A1
• Filed: 02/03/2015
• Published: 12/03/2015
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated (SK Hynix Inc.)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: HEBERT, Francois
• Granted Patent: US 9,368,389 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void.

Claims

1. A semiconductor device with voids within a silicon-on-insulator (SOI) structure comprising:

a semiconductor substrate;

an insulating layer disposed on the substrate;

a silicon-on-insulator (SOI) layer disposed on the insulating layer;

a device isolation layer and an active area disposed within the SOI layer;

one or more voids disposed within the insulating layer; and

a sealing insulating sealing an opening of the void.

2. The semiconductor device of claim 1, further comprising another insulating layer disposed on a surface of the void.

3. The semiconductor device of claim 2, wherein at least a part of a drain region, a source region, or a channel region of the active area is formed above an upper region of the void.

4. The semiconductor device of claim 1, further comprising a void protection layer disposed along sidewalls of the void.

5. The semiconductor device of claim 1, further comprising a protection layer disposed along sidewalls of the device isolation layer.

6. The semiconductor device of claim 1, comprising a protection layer and another insulating layer disposed between the device isolation layer and the void.

7. The semiconductor device of claim 1, wherein the semiconductor device comprises at least one of a CMOS (Complementary Metal-Oxide Semiconductor), an NMOS (N-type Metal-Oxide Semiconductor), a PMOS (P-type Metal-Oxide Semiconductor), an LDMOS (Laterally Diffused Metal-Oxide Semiconductor), a BJT (Bipolar Junction Transistor), a Diode, a Schottky diode, GaAs, InP, and GaN-based devices such as MESFETs, HEMTs, pHEMTs, MIS-HEMTs, or MOSFETs.

8. The semiconductor device of claim 1, wherein the void is filled with pure nitrogen or under vacuum.

9. The semiconductor device of claim 1, wherein a length of the void is longer than the a length of the opening.

10. A method of forming a semiconductor device with voids within a silicon-on-insulator (SOI) structure, the method comprising:

patterning on a silicon-on-insulator (SOI) substrate comprising an insulating layer between a substrate and an SOI layer;

forming a gap region by selectively etching the SOI layer and exposing the insulating layer;

etching the exposed insulating layer to form voids within the insulating layer; and

sealing the void.

11. The method of claim 10, wherein the voids extend laterally from the gap region formed in the SOI layer.

12. The method of claim 10, wherein the void is sealed by a thermal oxidation method or a chemical vapor deposition (CVD) method.

13. The method of claim 10, wherein the sealing of the void comprises filing the gap region with another insulating layer.

14. The method of claim 10, further comprising forming a device isolation layer on the SOI layer prior to the patterning on the SOI substrate.

15. The method of claim 14, wherein the forming of the device isolation layer comprises:

forming at least one trenches in the SOI layer through a mask process;

forming an anti-etching layer at sides of the at least one trench; and

filing the at least one trench with an insulating layer.

16. The method of claim 10, further comprising forming a void-protection layer on a surface of the void.

17. The method of claim 10, further comprising forming a device isolation layer on the SOI layer after the sealing of the void.

18. The method of claim 10, wherein the gap region is formed by an anisotropic etching method.