FIN FIELD-EFFCT TRANSISTORS AND FABRICATION METHOD THEREOF

• US 20150348966A1
• Filed: 05/27/2015
• Published: 12/03/2015
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: ZHAO, JIE, ZENG, YIZHI
• Granted Patent: US 9,368,497 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02219 the compound comprising silicon and nitrogen
• CPC Class Codes: H01L 21/02222 the compound being a silazane
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02326 into a nitride layer, e.g. changing SiN to SiON
• CPC Class Codes: H01L 21/02343 treatment by exposure to a liquid
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 : adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the semiconductor substrate. The method also includes forming dummy gates formed over side and top surfaces of the fins; forming a precursor material layer with a surface higher than top surfaces of the fins to cover the dummy gates and the semiconductor substrate; performing a thermal annealing process to convert the precursor material layer into a dielectric layer having a plurality of voids; and planarizing the dielectric layer to expose the top surfaces of the dummy gates. Further, the method also includes performing a post-treatment process using oxygen-contained de-ionized water on the planarized dielectric layer to eliminate the plurality of voids formed in the dielectric layer; removing the dummy gates to form trenches; and forming a high-K metal gate structure in each of the trenches.

Claims

1. A method for fabricating fin-field effect transistors, comprising:

providing a semiconductor substrate;

forming a plurality of fins on a surface of the semiconductor substrate;

forming dummy gates over side and top surfaces of the fins;

forming a precursor material layer to cover the dummy gates and the semiconductor substrate;

performing a thermal annealing process on the precursor material layer to convert the precursor material layer into a dielectric layer having a plurality of voids;

planarizing the dielectric layer with the plurality of voids to expose top surfaces of the dummy gates;

performing a post-treatment process using oxygen-contained de-ionized water onto the planarized dielectric layer to eliminate the plurality of voids formed in the dielectric layer;

removing the dummy gates to form trenches in the dielectric layer without voids; and

forming a high-K metal gate structure in each of the trenches.

2. The method according to claim 1, wherein:

the dielectric layer is of silicon oxide.

3. The method according to claim 2, wherein:

the precursor material layer contains silicon element and one or more of hydrogen element and nitrogen element.

4. The method according to claim 3, wherein:

the precursor material layer is formed by a flowable chemical vapor deposition process;

a precursor of the flowable chemical vapor deposition process includes one or more of SiH₄, Si₂H₄, SiCH₆, SiC₂H₈, SiC₃H₁₀, SiC₄H₁₂, Si(OC₂H₅)₄, C₆H₁₆O₃Si, C₈H₂₄O₄Si₄, (CH₃)₂SiHOSiH(CH₃)₂, C₁₂H₂₄O₄Si₄, C₁₂H₃₁NO₆Si₂, and C₅Hi₅NSi;

a flow rate of the precursor is in a range of approximately 150 sccm˜

1000 sccm;

a pressure of a reaction chamber of the flowable chemical vapor deposition process is in a range of approximately 0.15 Torr˜

5 Torr; and

a temperature of the reaction chamber is in a range of approximately 20°

C.˜

150°

C.

5. The method according to claim 4, wherein:

the thermal annealing process is a low temperature water steam thermal annealing process;

a temperature of the low temperature water steam thermal annealing process is in a range of approximately 200°

C.˜

600°

C.; and

a pressure of a chamber of the low temperature water steam thermal annealing process is in a range of approximately 1 Torr˜

200 Torr.

6. The method according to claim 4, wherein:

an oxygen source of the oxygen-contained de-ionized water are ozone ions.

7. The method according to claim 6, wherein:

a mass percentile of the ozone ions in the oxygen-contained de-ionized water is less than approximately 10%.

8. The method according to claim 6, wherein:

the post-treatment process is a soaking process;

a soaking time is less than approximately 20 mins; and

a soaking temperature is in a range of approximately 50°

C.˜

100°

C.

9. The method according to claim 1, wherein:

sidewalls are formed on side and top surfaces of the dummy gates; and

a contact etching stop layer is formed on the sidewalls and the dummy gates.

10. The method according to claim 9, wherein:

the contact etching stop layer is made of one or more of SiN, SiON, SiC, SiOCN, and SiOBN; and

a thickness of the contact etching stop layer is in a range of approximately 10 Å

˜

150 Å

.

11. The method according to claim 9, wherein:

the sidewalls are made of one or more of SiN, SiON, SiC, SiOCN, and SiOBN; and

a thickness of the sidewalls is in a range of approximately 10 Å

˜

100 Å

.

12. The method according to claim 1, wherein:

the dummy gates are made of polysilicon.

13. The method according to claim 12, wherein:

the dummy gates are removed by a wet etching process; and

an etching solution of the wet etching process is one of a KOH solution and Tetra Methyl-Amonium Hydroxide (TMAH) solution.

14. The method according to claim 1, wherein forming the fins and the dummy gates further includes:

etching the semiconductor substrate to form the plurality of fins;

forming an insulation material layer to cover the fins and the semiconductor substrate;

planarizing the insulation material layer using the top surfaces of the fins as a stop layer;

performing an etch back process to cause a top surface of the remaining insulation material layer to be lower than the top surfaces of the fins to form insulation layers between adjacent fins; and

forming the dummy gates on the top and side surfaces of the fins and a portion of surfaces of the insulation layer.

15. The method according to claim 1, after forming the precursor material layer, further including:

planarizing the precursor material layer to expose the dummy gate structures so as to reduce a thickness of the precursor material layer; and

performing a water steam thermal annealing process on the planarized precursor material layer.

16. A semiconductor structure having multiple fin field-effect transistors, comprising:

a semiconductor substrate;

a plurality of fins formed on a surface of the substrate;

an insulation layer with a surface lower than top surfaces of the fins formed on the surface of the substrate;

a high-K gate dielectric layer formed over the top surfaces and side surfaces of the fins and the surface of the insulation layer;

a metal gate formed on the high-K gate dielectric layer;

sidewalls formed on side surfaces of the high-K gate dielectric layer;

a contact etching stop layer formed on the side surfaces of the high-K dielectric layer and the surface of the insulation layer; and

a dielectric layer treated with oxygen-contained de-ionized water to eliminate a plurality of voids formed in the dielectric layer formed on the contact etching stop layer.

17. The semiconductor structure having multiple fin field-effect transistors according to claim 16, wherein:

the dielectric layer is formed by converting a precursor material layer by a thermal annealing process.

18. The semiconductor structure having multiple fin field-effect transistors according to claim 17, wherein:

the thermal annealing process is a low temperature water steam thermal annealing process.

19. The semiconductor structure having multiple fin field-effect transistors according to claim 16, wherein:

an oxygen source of the oxygen-contained de-ionized water are ozone ions.

20. The semiconductor structure having multiple fin field-effect transistors according to claim 16, wherein:

the dielectric layer is made of silicon oxide.