SEMICONDUCTOR DEVICE

• US 20150349113A1
• Filed: 02/27/2015
• Published: 12/03/2015
• Est. Priority Date: 05/28/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KATOH, Shunsuke, KAWAGUCHI, Yusuke, NOZU, Tetsuro
• Application Number:
  US14/634,387
• Publication Number:
  US 20150349113A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

According to one embodiment, a semiconductor device, includes a first semiconductor layer of a first conductivity, a second semiconductor layer of a second conductivity type, and a third semiconductor layer of the first conductivity. A first plurality of source elements are spaced from each other and a first gate electrode extends continuously between the source elements. A source electrode is electrically connected to the source elements, and a drain electrode is on the first semiconductor layer such that the first semiconductor layer is between the second semiconductor layer and the drain electrode. By employing this structure, an inactive region decreases, and an active area ratio increases. Thereby, a breakdown voltage can be maintained while an on-resistance can be reduced.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type on the first semiconductor layer;

a third semiconductor layer of the first conductivity type on the second semiconductor layer, the second semiconductor layer being between the first and third semiconductor layers in a first direction;

a first plurality of source elements each extending along the first direction from the third semiconductor layer into the second semiconductor layer and spaced from each other along a second direction perpendicular to the first direction;

a first gate electrode extending along the first direction from the third semiconductor layer into the second semiconductor layer and spaced from the first plurality of source elements in a third direction perpendicular to the first and second directions, the first gate electrode extending continuously along the second direction parallel to the first plurality of source elements;

a source electrode electrically connected to first plurality of source elements; and

a drain electrode on the first semiconductor layer such that the first semiconductor layer is between the second semiconductor layer and the drain electrode in the first direction.

2. The semiconductor device according to claim 1, further comprising:

a second plurality of source elements each extending along the first direction from the third semiconductor layer into the second semiconductor layer and spaced from each other along the second direction perpendicular, the second plurality of source elements spaced in the third direction from the first plurality of source elements and the first gate electrode such that the first gate electrode is between the first plurality of source elements and the second plurality of source elements.

3. The semiconductor device according to claim 2, wherein

spacing between source elements in the first plurality of source elements is at a first pitch along the second direction, and

spacing between source elements in the second plurality of source elements is at the first pitch along the second direction.

4. The semiconductor device according to claim 3, wherein the second plurality of source elements is offset in the second direction by one-half of the first pitch from the first plurality of source elements.

5. The semiconductor device according to claim 4, wherein the first gate electrode includes a plurality of portions which extend along the third direction such that a portion of the first gate electrode is between each adjacent pair of source elements in the first plurality of source elements and between each adjacent pair of source elements in the second plurality of source elements.

6. The semiconductor device according to claim 2, wherein the first gate electrode includes a plurality of portions which extend along the third direction such that a portion of the first gate electrode is between each adjacent pair of source elements in the first plurality of source elements and between each adjacent pair of source elements in the second plurality of source elements.

7. The semiconductor device according to claim 1, further comprising:

a gate insulating layer between the first gate electrode and the first, second, and third semiconductor layers; and

a source element insulating layer between each source element in the first plurality of source elements and the first, second, and third semiconductor layers.

8. The semiconductor device according to claim 1, wherein the source electrode is directly contacting each source element in the first plurality of source elements.

9. The semiconductor device according to claim 1, wherein the first plurality of source elements extends along the first direction into the first semiconductor layer for a first distance and the first gate electrode extends along the first direction into the first semiconductor layer for a second distance that is less than the first distance.

10. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

11. The semiconductor device according to claim 1, further comprising:

a second plurality of source elements each extending along the first direction from the third semiconductor layer into the second semiconductor layer and spaced from each other along the second direction perpendicular, the second plurality of source elements spaced in the third direction from the first plurality of source elements and the first gate electrode such that the first gate electrode is between the first plurality of source elements and the second plurality of source elements; and

a second gate electrode extending along the first direction from the third semiconductor layer into the second semiconductor layer and spaced from the first gate electrode and the second plurality of source elements in the third direction, the second gate electrode extending continuously along the second direction parallel to second plurality of source elements.

12. The semiconductor device according to claim 11, wherein

spacing between elements in the first plurality of source elements is at a first pitch along the second direction,

spacing between source elements in the second plurality of source elements along the second direction is at the first pitch, and

the second plurality of source elements is offset by one-half of the first pitch in the second direction from the first plurality of source elements.

13. The semiconductor device according to claim 12, wherein

the first gate electrode includes:

a plurality of first portions which extend along the third direction such that a first portion is between each adjacent pair of source elements in the first plurality of source elements, and

a plurality of second portions which extend along the third direction such that a second portion is between each adjacent pair of source elements in the second plurality of source elements, and

the first and second gate electrodes are electrically connected by the second portions.

14. The semiconductor device according to claim 11, wherein

the first gate electrode includes:

a plurality of first portions which extend along the third direction such that a first portion is between each adjacent pair of source elements in the first plurality of source elements, and

a plurality of second portions which extend along the third direction such that a second portion is between each adjacent pair of source elements in the second plurality of source elements, and

the first and second gate electrodes are electrically connected by the second portions.

15. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a first semiconductor layer of the first conductivity type on the semiconductor substrate;

a second semiconductor layer of a second conductivity type on the first semiconductor layer;

a third semiconductor layer of the first conductivity type on the second semiconductor layer;

a first trench penetrating the second and third semiconductor layers in a perpendicular direction to a surface of the semiconductor substrate;

a second trench penetrating the second and third semiconductor layers in the perpendicular direction to the surface of the semiconductor substrate, the second trench being separated from the first trench;

a third trench penetrating the second and third semiconductor layers in the perpendicular direction to the surface of the substrate, the third trench being separated from the second trench;

a first groove penetrating the second and third semiconductor layers in the perpendicular direction to the surface of the substrate, the first groove being provided in parallel with a direction connecting the first, second and third trenches in a plan view;

a first, second, and third insulating film formed in the first, second and third trenches, respectively;

a first, second and third conductive section formed in the first, second, and third trenches, and inside the first, second and third insulating films, respectively;

a source electrode electrically connected to the first, second, and third conductive sections, and on the third semiconductor layer;

a fourth insulating film formed in the first groove;

a gate electrode in the fourth insulating film; and

a drain electrode provided on a back surface side of the substrate.

16. The semiconductor device according to claim 15, further comprising:

a fourth trench penetrating the second and third semiconductor layers in the perpendicular direction to the surface of the substrate; and

a fifth trench penetrating the second and third semiconductor layers in the perpendicular direction to the surface of the substrate, the fifth trench being separated from the fourth trench, wherein

a direction connecting the fourth trench and the fifth trench in the plan view is parallel with the first groove, and

the first groove is formed between the first, second and third trenches, and the fourth and fifth trenches.

17. A semiconductor device, comprising:

a plurality of source elements arranged in a dotted pattern such that the source elements are separated from each other in a first plane of a first semiconductor layer of a first conductivity type, the source elements penetrating, in a first direction orthogonal to the first plane, a second semiconductor layer of a second conductivity type disposed on the first semiconductor and a third semiconductor layer of the first conductivity type disposed on the second semiconductor layer;

an insulating film adjacent to each source element and between each source element and the first, second, and third semiconductor layers;

a gate electrode in a plurality of grooves formed in an striped pattern spaced from each other in a second direction parallel to the first plane and extending along a third direction that is parallel to the first plane and perpendicular to the second direction, the grooves penetrating the second and third semiconductor layers in the first direction; and

a gate insulating film between the gate electrode and the first, second, and third semiconductor layers, wherein

the source elements are between the plurality of grooves.

18. The semiconductor device according to claim 17, wherein the plurality of source elements extend along the first direction into the first semiconductor layer for a first distance and the plurality of grooves extends along the first direction into the first semiconductor layer for a second distance that is less than the first distance.

19. The semiconductor device according to claim 17, wherein the dotted pattern of the plurality of source elements has rows and columns and each column of the dotted pattern is between a respective pair of adjacent grooves and each column of the dotted pattern is disposed with one-half pitch offset from each adjacent column of the dotted pattern.

20. The semiconductor device according to claim 17, further comprising:

a plurality of connector grooves extending between adjacent grooves of the plurality of grooves and electrically connecting portions of the gate electrode in adjacent grooves, the connector grooves passing between adjacent source elements in the dotted pattern.