TRANSISTOR STRUCTURE HAVING BURIED ISLAND REGIONS

• US 20150349124A1
• Filed: 05/07/2015
• Published: 12/03/2015
• Est. Priority Date: 05/07/2014
• Status: Active Grant

• Current Assignee: Finwave Semiconductor, Inc.
• Original Assignee: Cambridge Electronics, Inc.
• Inventors: Lu, Bin, Palacios, Tomas, Xia, Ling, Azize, Mohamed
• Granted Patent: US 10,566,192 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/861 : Diodes

Abstract

A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.

Claims

1. A transistor, comprising:

a source region;

a drain region;

a semiconductor region located between the source region and the drain region;

at least one island region located in the semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; and

a gate region located between the source region and the drain region covering at least a portion of the island regions.

2. The transistor of claim 1, wherein the semiconductor region comprises In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

3. The transistor of claim 2 wherein the semiconductor region further comprises at least one additional material and/or a heterostructure.

4. The transistor of claim 1, further comprising a second semiconductor layer located on the semiconductor region and covering a least a portion of the island regions.

5. The transistor of claim 4, wherein the second semiconductor layer comprises In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

6. The transistor of claim 1, wherein the semiconductor region includes a barrier layer located at a surface of the semiconductor region.

7. The transistor of claim 4, wherein the second semiconductor layer includes a barrier layer located at a surface of the second semiconductor layer.

8. The transistor of claim 6, wherein the barrier layer comprises at least one layer of In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si_xN_y, SiO₂, Ga₂O₃, ZnO₂ and/or etch-stop layers formed by a combination of these materials.

9. The transistor of claim 6, wherein the barrier layer has a recessed region under the gate region. The method of claim 5 wherein the second semiconductor layer further comprises at least one additional material and/or a heterostructure.

10. The transistor of claim 1, wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

11. The transistor of claim 1, wherein the gate region comprises a gate electrode located over the semiconductor region.

12. The transistor of claim 11, wherein the gate electrode comprises one or more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors or conductive oxides, and dielectric materials.

13. The transistor of claim 1, wherein the gate region comprises a gate dielectric layer located between the gate electrode and a surface of the semiconductor region.

14. The transistor of claim 13, wherein the gate dielectric layer comprises Al₂O₃, Si_xO_y, Si_xN_y, Si_xO_yN_z, Teflon, HfO₂, or any other dielectric with a dielectric constant below 200.

15. A diode, comprising:

a cathode region;

a semiconductor region;

at least one island region located in the semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; and

an anode region covering at least a portion of the island regions.

16. The diode of claim 15, wherein the semiconductor region comprises of In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

17. The diode of claim 16 wherein the semiconductor region further comprises at least one additional material and/or heterostructure.

18. The diode of claim 15, further comprising a second semiconductor layer located on the semiconductor region and covering at least a portion of the island regions.

19. The diode of claim 18, wherein the second semiconductor layer comprises In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

20. The diode of claim 19 wherein the second semiconductor layer comprises at least one additional material and/or heterostructure.

21. The diode of claim 15, wherein the semiconductor region includes a barrier layer located at a surface of the semiconductor region.

22. The diode of claim 18, wherein the second semiconductor layer includes a barrier layer located at a surface of the second semiconductor layer.

23. The diode of claim 21, wherein the barrier layer comprises at least one layer of In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si_xN_y, SiO₂, Ga₂O₃, ZnO₂ and/or etch-stop layers formed by a combination of these materials.

24. The diode of claim 21, wherein the barrier layer has a recessed region under the anode region.

25. The diode of claim 15 wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

26. The diode of claim 15, wherein the anode region includes an anode electrode located over the semiconductor region.

27. The diode of claim 26, wherein the anode electrode includes one or more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors or conductive oxides and dielectric materials.

28. The diode of claim 26, wherein the anode electrode and the semiconductor region are in electrical contact.

29. The diode of claim 26, wherein the anode region includes a dielectric layer located between the anode electrode and a surface of the semiconductor region.

30. The diode of claim 29, wherein the dielectric layer comprises Al₂O₃, Si_xO_y, Si_xN_y, Si_xO_yN_z, Teflon, HfO₂, or any other dielectric with a dielectric constant below 200.

31. A semiconductor structure, comprising:

a semiconductor region;

at least one island region located in the semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; and

a conductive electrode covering a least a portion of the island regions.

32. The semiconductor structure of claim 31 wherein the semiconductor region comprises In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

33. The semiconductor structure of claim 32 wherein the semiconductor region further includes at least one additional material and/or heterostructure.

34. The semiconductor structure of claim 31, further comprising a second semiconductor layer located on the semiconductor region and covering at least a portion of the island regions.

35. The semiconductor structure of claim 34, wherein the second semiconductor layer comprises In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

36. The semiconductor structure of claim 31 wherein the semiconductor region includes a barrier layer located at the surface of the semiconductor region.

37. The semiconductor structure of claim 34 wherein the second semiconductor layer includes a barrier layer located at the surface of the second semiconductor layer.

38. The semiconductor structure of claim 36, wherein the barrier layer comprises one or more layers of In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si_xN_y, SiO₂, Ga₂O₃, ZnO₂ and/or etch-stop layers formed by a combination of these materials.

39. The semiconductor structure of claim 36, wherein the barrier layer has a recessed region under the conductive electrode.

40. The semiconductor structure of claim 31 wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

41. The semiconductor structure of claim 31, wherein the conductive electrode comprises one more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors or conductive oxides and dielectric materials.

42. The semiconductor structure of claim 31, further comprising one or more dielectric layers located between the conductive electrode and the surface of the semiconductor region.

43. The semiconductor structure of claim 42, wherein the dielectric layer comprises Al₂O₃, Si_xO_y, Si_xN_y, Si_xO_yN_z, Teflon, HfO₂, or any other dielectric with a dielectric constant below 200.

44. A method of forming a semiconductor structure, the method comprising:

forming at least one island region in a semiconductor region, each of the island regions differing from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition; and

forming a conductive electrode covering at least a portion of the island regions.

45. The method of claim 44, wherein the semiconductor region comprises In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

46. The method of claim 45 wherein the semiconductor region includes at least one additional material and/or heterostructures.

47. The method of claim 44, further comprising forming a second semiconductor layer on the semiconductor region.

48. The method of claim 47, wherein the second semiconductor layer is formed by epitaxial regrowth, sputtering or wafer bonding.

49. The method of claim 47, wherein the second semiconductor layer comprises In_xAl_yGa_zN (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), SiC, In_xAl_yGa_zAs (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, x+y+z=1), diamond, Si and/or oxide semiconductors.

50. The method of claim 44, wherein forming the island regions comprises forming the island regions by ion-implantation, diffusion to change resistivity, doping type, doping concentration, and/or mechanical strain in the island regions.

51. The method of claim 44, wherein forming the island regions comprises forming the island regions by etching and re-deposition of crystalline, poly-crystalline, amorphous semiconductors, dielectric materials or voids containing no solid-phase material.

52. The method of claim 44, wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

53. The method of claim 44, wherein forming the conductive electrode comprises the deposition one or more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors and conductive oxides.

54. The method of claim 44, further comprising forming a dielectric layer between the conductive electrode and the surface of the semiconductor region.

55. The method of claim 44 wherein the semiconductor region includes a barrier layer located at the surface of the semiconductor region.

56. A method of forming a transistor having a tailored threshold voltage, the method comprising:

forming at least one island region in a semiconductor region, wherein forming the at least one island region includes selecting at least one structural and/or compositional characteristic for each of the island regions that differs from the at least one structural and/or compositional characteristic of the semiconductor region so that the transistor has the tailored threshold voltage, wherein forming the at least one island region includes forming the at least one island region with the selected structural and/or compositional characteristic; and

forming a conductive electrode covering at least a portion of the island regions.

57. The method of claim 56 wherein the at last one structural and/or compositional characteristic is selected from the group including resistivity, doping type, doping concentration, strain and material composition.