PROCESS FOR PREPARING A SEMICONDUCTOR STRUCTURE FOR MOUNTING

• US 20150349217A1
• Filed: 08/14/2015
• Published: 12/03/2015
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Koninklijke Philips N.V.
• Inventors: SUN, DECAI, SUN, CHARLENE, SHCHEKIN, OLEG
• Granted Patent: US 9,899,578 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2933/005 relating to encapsulations
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H01L 33/54 having a particular shape
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

Claims

1. A process for preparing a semiconductor structure for mounting to a carrier, the process comprising:

causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure;

causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

2. The process of claim 1 wherein causing the support material to substantially fill the void comprises causing a support material, which when solidified has a glass transition temperature greater than an operating temperature of the semiconductor structure, to substantially fill the void.

3. The process of claim 2 wherein causing the support material to substantially fill the void comprises causing a support material, which when solidified has a glass transition temperature of at least 195 degrees Celsius, to substantially fill the void.

4. The process of claim 1 wherein causing the support material to fill the void comprises causing a support material to at least partially overfill the void and further comprising planarizing the semiconductor structure such that an outer surface of the support material is substantially co-planar with an outer surface of the semiconductor structure.

5. The process of claim 4 wherein the planarizing comprises at least one of:

lapping the outer surfaces of the semiconductor structure and the support material;

polishing the outer surfaces of the semiconductor structure and the support material; and

plasma etching the outer surfaces of the semiconductor structure and the support material.

6. The process of claim 1 wherein causing the support material to substantially fill the void comprises causing the support material to substantially fill voids in a plurality of semiconductor structures located on a semiconductor wafer.

7. The process of claim 1 wherein causing the support material to substantially fill the void comprises at least one of:

causing the support material to substantially fill a via formed between regions of the semiconductor structure, the via facilitating electrical connection to the regions of the semiconductor structure; and

causing the support material to substantially fill an insulating trench formed in the semiconductor structure, the insulating trench being operable to electrically insulate portions of the semiconductor structure to facilitate electrical connection thereto.

8. The process of claim 1 causing the support material to substantially fill the void comprises spin coating the support material on the semiconductor structure.

9. The process of claim 8 further comprising curing the support material.

10. The process of claim 9 wherein the curing comprises at least one of:

causing a solvent in the support material to evaporate, thus at least partially solidifying the support material; and

heating the semiconductor structure to a temperature sufficient to cause the support material to at least partially solidify.

11. The process of claim 1 wherein causing the support material to substantially fill the void comprises causing a support material that further acts as a passivation layer to substantially fill the void, the passivation layer being operable to prevent contamination of the semiconductor structure during subsequent processing.

12. The process of claim 1 wherein the semiconductor structure is configured to emit light at a first wavelength and wherein causing the support material to substantially fill the void comprises causing a support material that is resistant to degradation by exposure to light of the first wavelength to substantially fill the void.

13. The process of claim 1 wherein causing the support material to substantially fill the void comprises causing a support material comprising one of:

a polyimide material;

a benzocyclobutene material;

a material comprising polyimide and epoxy; and

a material comprising polyimide and silicone, to substantially fill the void.

14. A process for mounting a semiconductor structure comprising the process of claim 1 and further comprising mounting the semiconductor structure to the carrier such that the solidified support material bears upon a portion of the carrier to permit the solidified support material to further support the semiconductor structure.

15. The process of claim 14 wherein the semiconductor structure comprises a substrate on which the semiconductor structure is formed and further comprising removing the substrate after mounting the semiconductor structure to the carrier.

16. The process of claim 14 wherein the semiconductor structure comprises a mounting surface located on an opposite side of the semiconductor structure to the substrate and wherein the mounting comprises introducing a plurality of spaced apart metal bonding members between the mounting surface and the carrier, the metal bonding members being operable to bond the semiconductor structure to the carrier.

17. The process of claim 16 wherein causing the support material to substantially fill the void comprises causing a support material, which when solidified has a thermal expansion coefficient sufficiently similar to a thermal expansion coefficient of the metal bonding members, to substantially fill the void, such that thermal induced stresses in the semiconductor structure are minimized when a temperature of the semiconductor structure changes.

18. The process of claim 16 wherein introducing the plurality of metal bonding members comprises forming the bonding members on the mounting surface and wherein causing the support material to substantially fill the void further comprises causing the support material to substantially fill spaces between the metal bonding members.

19. The process of claim 16 wherein introducing the plurality of metal bonding members comprises forming the bonding members on the carrier and further comprising:

causing a support material to substantially fill spaces between the metal bonding members;

causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

20. The process of claim 16 wherein forming the plurality of metal bonding members comprises forming a plurality bonding members comprising gold.

21. A semiconductor light emitting structure comprising:

a first conductivity type semiconductor material, a second conductivity type semiconductor material, and a light emitting region disposed between the first conductivity type semiconductor material and the second conductivity type semiconductor material;

at least one void in the semiconductor structure, the void being defined by surfaces formed in the semiconductor structure;

a support material in the void, the support material being sufficiently solidified to support the semiconductor structure when mounted to a carrier and having a glass transition temperature greater than an operating temperature of the semiconductor light emitting apparatus.

22. A semiconductor light emitting apparatus comprising the semiconductor structure of claim 21 and further comprising a carrier, the semiconductor structure being mounted to the carrier such that the solidified support material bears upon a portion of the carrier to permit the solidified support material to further support the semiconductor structure.