CIRCUITS AND METHODS FOR ELIMINATING REFERENCE SPURS IN FRACTIONAL-N FREQUENCY SYNTHESIS

• US 20150349788A1
• Filed: 05/21/2015
• Published: 12/03/2015
• Est. Priority Date: 04/26/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Namdar-Mehdiabadi, Ardeshir, Frenette, Darren Roger, Rogers, John William Mitchell
• Granted Patent: US 9,362,925 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/1978 using a cycle or pulse removing circuit
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Claims

1. (canceled)

2. A circuit comprising:

a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate a first signal based on the reference signal and the feedback signal; and

a compensation circuit configured to receive the first signal, the compensation circuit including a charging circuit, a charge pump, and a voltage-to-current converter positioned between the charging circuit and the charge pump, the compensation circuit further configured to generate a compensation signal based on the received first signal.

3. The circuit of claim 2 wherein the charge pump is configured to receive the first signal and generate a current signal to compensate for a phase difference between the reference signal and the feedback signal.

4. The circuit of claim 3 wherein the compensation circuit further includes a loop filter configured to receive the current signal and generate a corresponding voltage signal, the voltage signal being provided to a voltage controlled oscillator (VCO) in communication with the compensation circuit.

5. The circuit of claim 3 wherein the compensation signal includes the current signal having a pulse with a substantially constant width and an amplitude representative of the phase difference.

6. The circuit of claim 2 wherein the PFD is configured to generate an up signal or a down (dn) signal as the first signal, the up signal being generated when a phase of the reference signal leads a phase of the feedback signal, the dn signal being generated when a phase of the reference signal lags a phase of the feedback signal.

7. The circuit of claim 2 wherein the charging circuit includes a capacitance element, a charging switch configured to facilitate charging of the capacitance element in response to the first signal, and a drain switch configured to facilitate draining of the charge in the capacitance element.

8. The circuit of claim 3 wherein the voltage-to-current converter is configured to generate a control signal in response to a voltage of a capacitance element of the charging circuit, the charge pump configured to generate the current signal based on the control signal from the voltage-to-current converter.

9. The circuit of claim 6 wherein the charge pump includes a first current source configured to generate a positive current as the current signal for the up signal and a second current source configured to generate a negative current as the current signal for the dn signal.

10. The circuit of claim 6 wherein the current signal is modulated based on a combination of the up signal and a pulse signal or a combination of the dn signal and the pulse signal.

11. The circuit of claim 6 wherein the compensation circuit further includes a first switch in communication with a first current source configured to generate a positive current as the current signal for the up signal and a second switch in communication with a second current source configured to generate a negative current as the current signal for the dn signal, the first and second switches configured to be controlled to provide a modulation of the current signal.

12. The circuit of claim 6 wherein the charging circuit includes a capacitance element and the compensation circuit further includes a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the first switch or the second switch being engaged only when the capacitance element has a substantially full charge.

13. The circuit of claim 7 wherein the compensation circuit further includes a first switch configured to cause a positive current to be generated as the current signal and a second switch configured to cause a negative current to be generated as the current signal, the charging switch not being engaged if either of the first switch and the second switch is engaged.

14. The circuit of claim 6 wherein the compensation circuit further includes a first control block in communication with a first switch and a second control block in communication with a second switch, the first control block configured to generate a first enable pulse for the first switch based on a combination of the up signal and a pulse signal, the second control block configured to generate a second enable pulse for the second switch based on a combination of the dn signal and the pulse signal.

15. The circuit of claim 6 wherein the compensation circuit further includes a first control block configured to generate an internal signal that goes high with a rising edge of the up signal and low with a falling edge of the pulse signal and a second control block configured to generate an internal signal that goes high with a rising edge of the dn signal and low with the falling edge of the pulse signal, each of the first and second control blocks further configured to combine the internal signal with the pulse signal to yield an enable signal.

16. The circuit of claim 6 wherein the current signal is modulated based on a combination of the up signal and a pulse signal or a combination of the dn signal and the pulse signal, the pulse signal including a plurality of pulses, each pulse having a substantially constant width and going high with a falling edge of the reference signal.

17. The circuit of claim 2 further comprising a voltage-controlled oscillator (VCO) in communication with the compensation circuit and a divider circuit in communication with the VCO and the PFD, the VCO configured to generate an output signal based on the compensation signal, the divider circuit configured to receive the output signal from the VCO and generate an updated version of the feedback signal.

18. The circuit of claim 17 further comprising a sigma delta modulator (SDM) in communication with the divider circuit to form a loop, the loop being configured to allow the output signal to have an output frequency that is a non-integer multiple of the frequency of the reference signal.

19. The circuit of claim 2 wherein the circuit is a Frac-N phase-locked loop (PLL) circuit.

20. A method comprising:

receiving a reference signal and a feedback signal;

generating a first signal based on the reference signal and the feedback signal; and

with a compensation circuit including a charging circuit, a charge pump, and a voltage-to-current converter positioned between the charging circuit and the charge pump, generating a compensation signal based on the generated first signal.

21. A wireless device comprising:

an antenna configured to facilitate reception of a radio-frequency (RF) signal;

a receiver in communication with the antenna, the receiver configured to process the RF signal; and

a frequency synthesizer in communication with the receiver, the frequency synthesizer circuit having a circuit including a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal, the PFD further configured to generate a first signal based on the reference signal and the feedback signal, the circuit further including a compensation circuit configured to receive the first signal, the compensation circuit including a charging circuit, a charge pump, and a voltage-to-current converter positioned between the charging circuit and the charge pump, the compensation circuit configured to generate a compensation signal based on the first signal.