SYSTEMS AND METHODS FOR SIMULTANEOUS SAMPLING OF SERIAL DIGITAL DATA STREAMS FROM MULTIPLE ANALOG-TO-DIGITAL CONVERTERS (ADCS), INCLUDING IN DISTRIBUTED ANTENNA SYSTEMS

• US 20150351088A1
• Filed: 05/30/2014
• Published: 12/03/2015
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Corning Optical Communications LLC (Corning Incorporated)
• Original Assignee: Corning Optical Communications Wireless Ltd. (Corning Incorporated)
• Inventors: Gutman, Amit
• Granted Patent: US 9,357,551 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H04W 72/0446 Resources in time domain, e.g. slots or frames
• CPC Class Codes: H04W 72/51 based on terminal or device properties
• CPC Class Codes: H04W 88/085 Access point devices with remote components

Abstract

Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.

Claims

1. A system for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), comprising:

a controller unit, comprising;

a chip select output port, a clock output port, and a plurality of data input ports each configured to receive a serial digital data stream; and

a processor configured to;

communicate a chip select signal on the chip select output port to receive a serial digital data stream on each of the plurality of data input ports simultaneously; and

communicate a clock signal on the clock output port; and

a plurality of ADCs, each ADC among the plurality of ADCs comprising;

a chip select input port electrically coupled to the chip select output port of the controller unit;

a clock input port electrically coupled to the clock output port of the controller unit; and

a data output port electrically coupled to a corresponding data input port among the plurality of data input ports of the controller unit;

the ADC configured to provide a serial digital data stream on the data output port in response to receiving the clock signal on the clock input port, if the chip select signal is present on the chip select input port.

2. The system of claim 1, wherein the controller unit further comprises a plurality of general purpose input/output (GPIO) pins comprising:

a first GPIO pin configured as the chip select output port;

a second GPIO pin configured as the clock output port; and

a plurality of other GPIO pins configured as the plurality of data input ports.

3. The system of claim 1, wherein each ADC among the plurality of ADCs is further configured to provide the serial digital data stream on the data output port according to a serial peripheral interface (SPI) protocol.

4. The system of claim 1, wherein each ADC among the plurality of ADCs further comprises a data input port electrically coupled to a data output port of the controller unit, and each ADC among the plurality of ADCs is further configured to determine a channel to convert based on a signal received on the data input port.

5. The system of claim 1, wherein each ADC among the plurality of ADCs is further configured to receive an analog signal from a power detector and convert the analog signal received from the power detector to provide the serial digital data stream.

6. The system of claim 1, further comprising a plurality of power detectors, wherein:

each power detector among the plurality of power detectors is disposed at a point in a distributed antenna system (DAS);

each power detector among the plurality of power detectors detects a power of a communications signal at the point in the distributed antenna system; and

each ADC among the plurality of ADCs is further configured to receive an analog signal from a corresponding power detector and convert the analog signal received from the power detector to provide the serial digital data stream.

7. The system of claim 6, wherein each power detector among the plurality of power detectors detects a radio frequency (RF) power level of a frequency that is different from the frequency detected by the other power detectors among the plurality of power detectors.

8. The system of claim 6, wherein the distributed antenna system is configured to provide communications services based on a Long Term Evolution (LTE) standard.

9. The system of claim 1, wherein the controller unit is further configured to receive the serial digital data stream on each of the plurality of data input ports at a data rate of at least 1.6 megabits per second (Mbps) and each ADC among the plurality of ADCs is further configured to provide the serial digital data stream on the each of the plurality of data output ports at a data rate of at least 1.6 Mbps.

10. The system of claim 1, wherein the controller unit is further configured to receive the serial digital data stream on each of the plurality of data input ports simultaneously within 50 microseconds (μ

s).

11. A method for simultaneously sampling serial digital data streams from multiple analog-to-digital converters (ADCs), comprising:

communicating a chip select signal to a plurality of chip select input ports in a corresponding plurality of ADCs to simultaneously activate the plurality of ADCs;

communicating a clock signal to a corresponding plurality of clock input ports in the plurality of ADCs;

simultaneously receiving a plurality of serial digital data streams from the corresponding plurality of ADCs in a corresponding data input port among a plurality of data input ports; and

simultaneously sampling the plurality of serial digital data streams received in the plurality of data input ports from the plurality of ADCs.

12. The method of claim 11, wherein:

communicating the clock signal comprises communicating the clock signal comprising clock pulses to a plurality of clock input ports in the plurality of ADCs; and

simultaneously sampling the plurality of serial digital data streams further comprises simultaneously sampling one bit from each of the plurality of serial digital data streams for each clock pulse of the clock signal.

13. The method of claim 11, further comprising communicating a configuration signal on a data input port of each ADC of the plurality of ADCs to configure which channel of the corresponding ADC to convert, prior to simultaneously receiving the plurality of serial digital data streams.

14. The method of claim 11, further comprising communicating a configuration signal on a data input port of each ADC of the plurality of ADCs to configure a number of bits for the corresponding ADC to provide in the serial digital data stream, prior to simultaneously receiving the plurality of serial digital data streams.

15. The method of claim 11, further comprising communicating a configuration signal on a data input port of each ADC of the plurality of ADCs to configure a method of conversion for the corresponding ADC to provide in the serial digital data stream, prior to simultaneously receiving the plurality of serial digital data streams.

16. The method of claim 11, further comprising not communicating the chip select signal on the chip select input port of each ADC among the plurality of ADCs.

17. A distributed antenna system (DAS), comprising:

a plurality of communications components, comprising;

a central unit configured to receive a downlink communications signal from a communications system and distribute the downlink communications signal over at least one downlink communications medium to a plurality of remote units;

each remote unit among the plurality of remote units configured to receive the downlink communications signal from the central unit over the at least one downlink communications medium and distribute the downlink communications signal to a client device;

a controller unit, comprising;

a chip select output port, a clock output port, and a plurality of data input ports each configured to receive a serial digital data stream; and

a processor configured to;

communicate a chip select signal on the chip select output port to receive a serial digital data stream on each of the plurality of data input ports simultaneously; and

communicate a clock signal on the clock output port; and

a plurality of signal detectors associated with at least one of the plurality of communications components, wherein each signal detector among the plurality of signal detectors comprises;

an interface to receive at least a portion of an analog communications signal from the DAS; and

an analog-to-digital converter (ADC) comprising;

a chip select input port electrically coupled to the chip select output port of the controller unit;

a clock input port electrically coupled to the clock output port of the controller unit; and

a data output port electrically coupled to a corresponding data input port among the plurality of data input ports of the controller unit;

the ADC configured to;

receive an analog signal from the corresponding signal detector; and

convert the analog signal to provide the serial digital data stream on the data output port in response to receiving the clock signal on the clock input port, if the chip select signal is present on the chip select input port.

18. The system of claim 17, wherein the central unit is further configured to receive an uplink communications signal from the plurality of remote units over at least one uplink communications medium and distribute the uplink communications signal to the communications system;

and each remote unit among the plurality of remote units is configured to receive the uplink communications signal from the client device and distribute the uplink communications signal to the central unit over the at least one uplink communications medium.

19. The system of claim 17, wherein each signal detector among the plurality of signal detectors is a power detector.

20. The system of claim 19, wherein each analog signal received from the power detector corresponding to each ADC among the plurality of ADCs operates to detect power in a different frequency band.

21. The system of claim 17, wherein the DAS is configured to provide communications services based on a Long Term Evolution (LTE) standard.

22. The system of claim 17, wherein the controller unit is further configured to receive the serial digital data stream on each of the plurality of data input ports at a data rate of at least 1.6 megabits per second (Mbps) and each ADC among the plurality of ADCs is further configured to provide the serial digital data stream on the data output port at a data rate of at least 1.6 Mbps.

23. The system of claim 17, wherein the controller unit is further configured to receive the serial digital data stream on each of the plurality of data input ports simultaneously within 50 microseconds (μ

s).