TESTING INTERPOSER METHOD AND APPARATUS

• US 20150355232A1
• Filed: 08/14/2015
• Published: 12/10/2015
• Est. Priority Date: 06/20/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Granted Patent: US 9,671,426 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B05C 21/00 Accessories or implements for use in connection with applying liquids or other fluent materials to surfaces, not provided for in groups B05C1/00 - B05C19/00 accessories or implements for use in connection with painting or artistic drawing and fully provided for in B44D3/02 - B44D3/38, see subgroups of B44D3/00
• CPC Class Codes: B44D 3/126 Paint roller trays
• CPC Class Codes: G01R 1/0416 Connectors, terminals G01R1/0425 and G01R1/0433 take precedence; with measurement function for battery poles G01R31/364
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence

Abstract

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Claims

1. An electrical device comprising;

(A) an integrated circuit die having functional circuitry and test circuitry, the die having through silicon input vias and through silicon output vias coupled to the functional circuitry and the test circuitry, the integrated circuit die having a first face and the through silicon vias having contact points on the first face; and

(B) a test interposer having a first face and a second face, the test interposer having through silicon input vias and through silicon output vias with contact points on the first and second faces, the contact points on the first face of the interposer being coupled with contact points on the first face of the integrated circuit die, the test interposer including;

(1) a first multiplexer having a first input coupled with the through silicon input vias of the test interposer, a control input, and an output coupled with the through silicon input vias of the integrated circuit die;

(2) a second multiplexer having a first input coupled with the through silicon input vias of the test interposer, a control input, and an output coupled with the through silicon input vias of the integrated circuit die;

(3) response collector circuitry having an input coupled with a through silicon via of the integrated circuit, a control input, and an output; and

(4) test access port circuitry having a test data input, a test clock input, a test mode select input, and a test data output, the test access port circuitry having control leads coupled to the first multiplexer, the second multiplexer, and the response collector, and an input coupled to the output of the response collector.

2. The device of claim 1 in which the test access port circuitry includes:

(A) a state machine having a clock input coupled with the test clock input, a mode input coupled with the test mode select input, and control outputs,

(B) an instruction register having a data input coupled with the test data input, a data output, and a control input coupled with a control output of the state machine,

(C) a data register having a data input coupled with the test data input, a data output, and a control input coupled with a control output of the state machine, and

(D) multiplexer circuitry having a first input coupled with the data output of the instruction register, a second input coupled with the data output of the data register, a control input coupled with a control output of the state machine, and a data output coupled with the test data output.

3. The device of claim 1 in which the contact points on the first face of the interposer are directly connected with contact points on the first face of the integrated circuit die.

4. The device of claim 1 including another integrated circuit die between the first face of the integrated circuit die and the test interposer and in which the contact points on the first face of the interposer are coupled with contact points on the first face of the integrated circuit die through the another integrated circuit die.

5. The device of claim 1 including a substrate, the test interposer is mounted in the substrate, and the second face of the test interposer faces the substrate.

6. The device of claim 1 in which the test access port circuitry includes a state machine having a clock input coupled with the test clock input, a mode input coupled with the test mode select input, and control outputs, the state machine operating through states of Test Logic Reset, Run Test Idle, Select-DR And Select-IR.