DATA STORAGE LAYOUT

• US 20150356009A1
• Filed: 05/18/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wheeler, Kyle B., Finkbeiner, Timothy P.
• Granted Patent: US 9,779,019 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.

Claims

1. A method for storing data elements comprising:

storing, in an array of memory cells in accordance with a particular storage layout, a plurality (M) of data elements to have a number (L) of logical operations performed thereon in parallel without performing a sense line address access;

wherein the particular storage layout is based on a quantity of compute components coupled to the memory array.

2. The method of claim 1, wherein each of the M data elements comprises N bits.

3. The method of claim 2, wherein the particular storage layout is horizontal if L is less than or equal to the quantity of the plurality of compute components divided by N.

4. The method of claim 3, wherein the particular storage layout is vertical if L is greater than the quantity of compute components.

5. The method of claim 1, wherein the particular storage layout is based, at least partially, on the quantity of bits in each of the M data elements.

6. The method of claim 1, wherein the particular storage layout is based, at least partially, on the type of the logical operation.

7. The method of claims 1, wherein each of the plurality of compute components is coupled to a pair of complementary sense lines.

8. The method of claim 1, wherein the logical operation is performed using the plurality of compute components.

9. The method of claim 2, wherein the plurality of compute components are coupled to a number of sense lines that are coupled to the plurality of memory cells.

10. The method of claims 5, wherein the particular memory layout maximizes the number of compute components used in performing the number of logical operations in parallel.

11. An apparatus comprising:

a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line wherein the first address space is configured to store a logical representation of a first portion of a value;

a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line wherein the second address space is configured to store a logical representation of a second portion of the value;

sensing circuitry configured to;

receive the value; and

perform a logical operation using the value without performing a sense line address access.

12. The apparatus of claim 11, wherein the value comprises a first value and further comprising:

a third address space of the memory array comprising a third number of memory cells coupled to the plurality of sense lines and a third select line wherein the third address space is configured to store the first portion of the logical representation of a second value; and

a fourth address space of the memory array comprising a fourth number of memory cells coupled to the plurality of sense lines and a fourth select line wherein the fourth address space is configured to store a second portion of the logical representation of the second value.

13. The apparatus of claim 12, wherein the sensing circuitry being configured to perform the logical operation comprises the sensing circuitry being configured to:

receive the second value;

perform a first portion of the logical operation using the second portion of the logical representation of the first value and a second portion of a logical representation of the second value; and

perform a second portion of the logical operation using the first portion of the logical representation of the first value, a first portion of the logical representation of the second value, and the result of performing the first portion of the logical operation.

14. The apparatus of claim 13, wherein the sensing circuitry being configured to perform the logical operation comprises the sensing circuitry being configured to:

perform the first portion of the logical operation using, as input, each of a first number of bits from the second portion of the logical representation of the first value and an associated second number of bits from the second portion of a logical representation of the second value; and

perform the second portion of the logical operation using, as input, each of a third number of bits from the first portion of the logical representation of the first value and an associated fourth number of bits from a first portion of the logical representation of the second value, and the result of the first portion of the logical operation.

15. The apparatus of claim 14, wherein the first number of bits are associated with the second number of bits and the third number of bits are associated with the fourth number of bits when the first number of bits and the second number of bits are stored in memory cells that are coupled to a same sense line from the plurality of sense lines.

16. The apparatus of claim 13, wherein the result of the first portion of the logical operation includes a carry bit.

17. The apparatus of claim 16, wherein the carry bit is moved from a first compute component associated with the second portion of the logical operation to a second compute component associated with the first portion of the logical operation.

18. The apparatus of claim 17, wherein the first compute component is coupled to a first sense line from the number of sense lines and wherein the second compute component is coupled to a second sense line from the number of sense lines.

19. An apparatus comprising:

a first address space of a memory array comprising a first plurality of memory cells coupled to a first plurality of sense lines and to a first select line wherein the first address space is configured to store a first portion of a logical representation of a first value;

a second address space of the memory array comprising a second plurality of memory cells coupled to a second plurality of sense lines and to a second select line wherein the second address space is configured to store a second portion of the logical representation of the first value;

sensing circuitry configured to;

receive the first value and a second value;

perform a logical operation without performing a sense line address access by;

performing a first portion of the logical operation using the second portion of the logical representation of the first value and a second portion of a logical representation of the second value; and

performing a second portion of the logical operation using the first portion of the logical representation of the first value, a first portion of the logical representation of the second value, and the result of the first portion of the logical operation.

20. The apparatus of claim 19, further comprising:

a third address space of the memory array comprising a third plurality of memory cells coupled to the first plurality of sense lines and a third select line wherein the third address space is configured to store the first portion of the logical representation of the second value; and

a fourth address space of the memory array comprising a fourth plurality of memory cells coupled to the second plurality of sense lines and a fourth select line wherein the fourth address space is configured to store the second portion of the logical representation of the first value.

21. The apparatus of claim 20, wherein at least one of the first plurality of sense lines is included in the second plurality of sense lines.

22. The apparatus of claim 21, wherein not all of the first plurality of sense lines are included in the second plurality of sense lines.

23. The apparatus of claim 21, wherein the result of the first portion of the logical operation includes a carry bit.

24. The apparatus of claim 23, wherein the carry bit is not moved from a first compute component associated with the second portion of the logical operation to a second compute component associated with the first portion of the logical operation.

25. The apparatus of claim 24, wherein the carry bit is included in the second portion of the logical operation via the at least one of the first plurality of sense liens that is included in the second plurality of sense lines.

26. A method for determining a data storage layout a memory layout comprising:

determining a storage layout of a plurality (M) of data elements, each data element comprising N-bits, in a memory array based on N, a number of logical operations to be performed in parallel, and a quantity of compute components coupled to the memory array;

storing a logical representation of each of the M data elements in a number of memory cells that are coupled to;

a sense line and a number of select lines if a first layout is determined;

a number of sense lines and a select line if a second layout is determined; and

the number of sense lines and the number of select lines if a third layout is determined; and

performing a plurality of logical operations in parallel using the M data elements.

27. The method of claim 26, wherein the first layout is a vertical layout, the second layout is a horizontal layout, and the third layout is a hybrid layout.

28. The method of claim 27, further comprising determining first and second threshold numbers of logical operations to be performed in parallel based on:

N; and

the quantity of the plurality of compute components coupled to the memory array.

29. The method of claim 28, wherein determining the first threshold number of logical operations includes:

dividing the quantity of compute components coupled to the memory array by N;

setting the result of the division equal to the first threshold number of logical operations.

30. The method of claim 29, wherein determining the second threshold number of logical operations includes setting the second number of logical operations equal to the quantity of compute components coupled to the memory array.

31. The method of claim 30, wherein determining the layout includes determining the horizontal layout if the number of logical operations to be performed in parallel is less than or equal to the first threshold number of logical operations.

32. The method of claim 31, wherein determining the layout includes determining the vertical layout if the number of logical operations to be performed in parallel is greater than or equal to the second threshold number of logical operations.

33. The method of claim 32, wherein determining the layout includes determining the hybrid layout if the number of logical operations to be performed in parallel is greater than the first threshold number of logical operations and less than the second threshold number of logical operations.

34. The method of claims 26, wherein performing the plurality of logical operations using the M data elements includes performing the plurality of logical operations in parallel using the quantity of compute components.

35. The method of claim 34, wherein determining the storage layout includes maximizing a number of the quantity of compute components used at a same time to perform the number of logical operations in parallel.