VIRTUAL ADDRESS TABLE

• US 20150356022A1
• Filed: 05/15/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Leidel, John D., Wheeler, Kyle B.
• Granted Patent: US 9,910,787 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57

Abstract

The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises: an instruction comprising a number of arguments; and an address table comprising a number of indexed address elements. Each one of the number of indexed address elements can correspond to a virtual address of a respective one of the number of arguments, wherein the address table can serves as a target for the number of arguments. The method can include storing the object file in a memory.

Claims

1. A method, comprising:

generating an object file comprising;

an instruction comprising a number of arguments; and

an address table comprising a number of indexed address elements;

wherein each one of the number of indexed address elements corresponds to a virtual address of a respective one of the number of arguments, and wherein the address table serves as a target for the number of arguments; and

storing the object file in a memory.

2. The method of claim 1, further comprising executing the object file;

wherein executing the object file comprises populating the indexed address elements of the address table with the virtual addresses corresponding to the respective number of arguments; and

wherein the indexed address elements are not populated with the virtual addresses corresponding to the respective number of arguments prior to executing the object file.

3. The method of claim 1, further comprising executing the instruction, wherein the instruction comprises an instruction for performing a number of operations involving the number of arguments without transferring data corresponding to the arguments, from a memory array in which the arguments are stored, to an external register.

4. The method of claim 3, wherein the number of arguments correspond to a respective number of vectors, and wherein executing the instruction comprises performing a number of logical operations using the number of vectors.

5. The method of claim 4, wherein performing the number of logical operations comprises performing at least one of:

an arithmetic operation; and

a compare operation.

6. The method of claim 1, wherein the object file further comprises a number of additional instructions, wherein arguments to the number of additional instructions comprise a number of external register indices.

7. The method of claim 1, wherein the instruction is one of multiple instructions of the object file, and wherein the method further comprises generating an address table for each of the respective multiple instructions.

8. The method of claim 1, further comprising populating, at runtime, the number of indexed address elements of the address table with the virtual addresses corresponding to the respective number of arguments.

9. The method of claim 8, further comprising translating, via a controller, the virtual addresses corresponding to the respective number of arguments to respective physical row and/or column addresses of a particular memory array, wherein the controller is external to a memory device comprising the particular memory array.

10. The method of claim 9, further comprising:

generating, via the controller, an instruction block to be dispatched from the controller to the memory device, the instruction block comprising;

a location of the address table;

an operation code corresponding to the instruction; and

the address table indices corresponding to the respective number of arguments corresponding to the instruction;

dispatching the instruction block to a control component of the memory device for execution of the instruction; and

providing a response to a host external to the memory device indicating whether the instruction was executed.

11. A method, comprising:

executing an object file stored in memory, wherein the object file comprises;

an instruction whose arguments are indices of a table of indexed address elements, with each index corresponding to a particular one of the arguments; and

the table of indexed address elements; and

populating the indexed address elements of the table, upon execution of the object file, with the virtual addresses of the arguments to which they correspond;

generating an instruction block that conforms to a particular instruction set architecture specification corresponding to a particular instruction type of the instruction.

12. The method of claim 11, further comprising dispatching the instruction block to a memory device comprising an array of memory cells from a controller external to the memory device, wherein the instruction block comprises:

a location of the populated table;

an operation code corresponding to the instruction; and

the indices corresponding to the arguments.

13. The method of claim 11, wherein dispatching the instruction block to the memory device comprises providing the instruction block to a control component of the memory device configured to control execution of the instruction;

and

wherein the particular instruction type corresponds to instructions executed to perform operations on operands stored in an array of memory cells of a memory device without transferring the operands to an external register.

14. The method of claim 11, further comprising initiating execution of the object file via a host external to a memory device comprising an array in which the object file is stored.

15. An apparatus, comprising:

an array of memory cells storing an object file, wherein the object file comprises;

for each one of a number of instructions of a particular instruction type, a respective address table comprising a number of indexed address elements;

wherein each one of the number of indexed address elements of a respective address table corresponds to a virtual address of one of a number of arguments corresponding to a respective instruction; and

wherein the number of indexed address elements are configured to be populated with appropriate corresponding virtual addresses upon execution of the object file.

16. The apparatus of claim 15, wherein the object file is a relocatable object file.

17. The apparatus of claim 15, wherein the number of instructions of the particular instruction type are instructions to be executed in a memory array in-situ.

18. The apparatus of claim 17, wherein the object file further comprises a number of instructions of a different particular instruction type, and wherein the number of instructions of the different particular instruction type have corresponding arguments that are indices of registers external to the array.

19. The apparatus of claim 15, further comprising a host external to a memory device comprising the array of memory cells and configured to populate the number of indexed address elements with the appropriate virtual addresses at runtime.

20. The apparatus of claim 15, further comprising a channel controller external to a memory device comprising the array of memory cells, wherein the channel controller is configured to:

translate the populated virtual addresses in the address table to physical rows and columns of the memory array; and

populate a dispatch block with a location in the memory array of at least one of the address tables.

21. An apparatus, comprising:

a host;

a memory device coupled to the host, wherein the memory device comprises an array of memory cells configured to store an object file;

wherein the host is configured to initiate execution of the object file, the object file comprising;

an instruction comprising a number of arguments; and

an address table comprising a number of indexed address elements;

wherein each one of the number of indexed address elements corresponds to a virtual address of a respective one of the number of arguments, and wherein the address table serves as a target for the number of arguments.

22. The apparatus of claim 21, wherein the host is configured to populate, at runtime, the address elements with virtual addresses corresponding to the number of arguments.

23. The apparatus of claim 22, wherein the host comprises a channel controller configured to translate the virtual addresses corresponding to the number of arguments to physical locations in the memory array prior to providing an instruction dispatch block to the memory device.

24. The apparatus of claim 21, wherein the instruction is an instruction whose corresponding machine level instruction set architecture accepts physical row/column indices as instruction arguments and does not accept indices to external functional units as instruction arguments.

25. The apparatus of claim 21, wherein the host is configured to:

generate an instruction dispatch block; and

provide the instruction dispatch block to a control component of the memory device, wherein the control component is configured to perform a number of operations corresponding to the instruction on a number of operands stored in the array, and wherein the number of operands are stored in the array at row and column locations indicated in the address table.

26. The apparatus of claim 25, wherein the instruction dispatch block comprises:

a location of the address table in the memory array;

an operation code corresponding to the instruction; and

a number of indices of the address table corresponding to the arguments.

27. An apparatus, comprising:

a host configured to generate an object file; and

a memory device comprising an array of memory cells configured to store the object file, wherein the object file comprises;

an object code instruction comprising a number of arguments; and

an address table comprising a number of indexed address elements; and

wherein the number of arguments of the object code instruction are respective indices of the address table, and wherein the number of address elements represent addresses to be populated at runtime and corresponding to a respective number of source code arguments.

28. The apparatus of claim 27, wherein the host is configured to:

populate the address elements with virtual addresses corresponding to the number of source code arguments; and

translate the virtual addresses to physical rows and columns prior to dispatching an instruction block corresponding to the object code instruction to the memory device.

29. The apparatus of claim 27, further comprising a channel controller that is external to the memory device and comprises a translation component configured to perform virtual address to physical address translation and dispatch an instruction block corresponding to the object code instruction to the memory device.

30. The apparatus of claim 29, wherein the host is external to the memory device and coupled thereto via a memory channel, and wherein the host comprises:

a processor comprising a number of registers; and

the channel controller.

31. The apparatus of claim 30, wherein the object code instruction corresponds to a number of arithmetic operations to be performed on operands stored in the memory array without transferring the operands to the number of registers.