DATA PROCESSOR AND METHOD FOR DATA PROCESSING

• US 20150356054A1
• Filed: 01/10/2013
• Published: 12/10/2015
• Est. Priority Date: 01/10/2013
• Status: Abandoned Application

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: BARAK, Itzhak, AMIR, Aviram, BEN ZEEV, Eliezer
• Application Number:
  US14/759,205
• Publication Number:
  US 20150356054A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8061 Details on data memory access
• CPC Class Codes: G06F 7/764 Masking
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register

Abstract

A integrated circuit device has at least one instruction processing module arranged for executing vector data processing upon receipt of a respective one of a set of data processing instructions. The data processing instructions include at least one matrix processing instruction for processing elements of a matrix. The elements of rows of the matrix are stored in a set of register, and the instruction processing module comprising an accessing unit for accessing selected elements of the matrix, which selected elements are non-sequentially located according to a predetermined pattern across multiple registers of the set of registers, the accessing enabling respective processing lanes to write or read different registers. Advantageously elements in columns of a matrix can efficiently be processed.

Claims

1. An integrated circuit device comprising:

at least one instruction processing module arranged for executing vector data processing upon receipt of a respective one of a set of data processing instructions, the data processing instructions comprising at least one matrix processing instruction for processing elements of a matrix, the elements of rows of the matrix being stored in a set of registers, and the instruction processing module comprising an accessing unit for accessing selected elements of the matrix, which selected elements are non-sequentially located according to a predetermined pattern across multiple registers of the set of registers, the accessing enabling respective processing lanes to write or read different registers.

2. Device as claimed in claim 1, wherein the predetermined pattern determines accessing the selected elements according to a column of the matrix.

3. Device as claimed in claim 1, wherein the matrix is a two-dimensional matrix.

4. Device as claimed in claim 1, wherein the matrix processing instruction comprises an indication of the predetermined pattern.

5. Device according to claim 1, wherein the size of the matrix row is 2ⁿ, wherein n is an integer and 2ⁿ is two to the power n.

6. Device as claimed in claim 5, wherein the size of the matrix column is 2ⁿ.

7. Device as claimed in claim 5, wherein n is 2, 3 or 4 and the matrix is a two-dimensional matrix of a matrix size 4×

4, 8×

8 or 16×

16 respectively.

8. Device according to claim 1, wherein the matrix processing instruction comprises an indication of the matrix row and/or column size.

9. Device as claimed in claim 1, wherein the at least one matrix processing instruction comprises a load instruction according to the predetermined pattern, a store instruction according to the predetermined pattern, or an add instruction according to the predetermined pattern.

10. Device as claimed in claim 1, wherein the at least one instruction processing module comprises multiple instruction processing modules.

11. Method of instruction processing arranged for executing vector data processing upon receipt of a respective one of a set of data processing instructions, the data processing instructions comprising at least one matrix processing instruction for processing elements of a matrix, the elements of rows of the matrix being stored in a set of registers, and the instruction processing comprising accessing selected elements of the matrix, which selected elements are non-sequentially located according to a predetermined pattern across multiple registers of the set of registers.

12. Method as claimed in claim 11, wherein the predetermined pattern determines accessing the selected elements according to a column of the matrix.

13. Method as claimed in claim 11, wherein the matrix is a two-dimensional matrix.

14. Method as claimed in claim 11, wherein the matrix processing instruction comprises an indication of the predetermined pattern.

15. Method according to claim 11, wherein the size of the matrix row is 2ⁿ, wherein n is an integer and 2ⁿ is two to the power n.

16. Method as claimed in claim 15, wherein the size of the matrix column is 2ⁿ.

17. Method as claimed in claim 15, wherein n is 2,3 or 4 and the matrix is a two-dimensional matrix of a matrix size 4×

4, 8×

8 or 16×

16 respectively.

18. Method according to claim 11, wherein the matrix processing instruction comprises an indication of the matrix row and/or column size.

19. Method as claimed in claim 11, wherein the at least one matrix processing instruction comprises one of a group consisting of:

a load instruction according to the predetermined pattern, a store instruction according to the predetermined pattern, and an add instruction according to the predetermined pattern.

20. A tangible computer program product comprising instructions for causing a processor system to perform vector data processing upon receipt of a respective one of a set of data processing instructions, the data processing instructions comprising at least one matrix processing instruction for processing elements of a matrix, the elements of rows of the matrix being stored in a set of registers, and the instruction processing comprising accessing selected elements of the matrix, which selected elements are non-sequentially located according to a predetermined pattern across multiple registers of the set of registers.