APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY

• US 20150357007A1
• Filed: 05/15/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Murphy, Richard C.
• Granted Patent: US 9,704,540 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.

Claims

1. A method, comprising:

protecting a number of data values stored in a respective number of memory cells coupled to a sense line of an array via a parity value corresponding to the number of data values that is determined without transferring data from the array via an input/output (I/O) line; and

storing the parity value in another memory cell coupled to the sense line.

2. The method of claim 1, wherein protecting the number of data values comprises performing, using sensing circuitry, exclusive OR (XOR) operations on the number of data values stored in the respective number of memory cells to determine the parity value.

3. The method of claim 2, wherein performing the XOR operations without transferring data from the array via an I/O line comprises performing the XOR operations without performing a sense line address access.

4. The method of claim 1, further comprising updating the parity value responsive to updated data being written to a particular memory cell of the number of memory cells.

5. The method of claim 4, wherein updating the parity value includes removing, from the parity value determination, the data value stored in the particular memory cell.

6. The method of claim 5, wherein removing, from the parity value determination, the data value stored in the particular memory cell comprises:

sensing the data value stored in the particular memory cell;

performing an XOR operation on the data value stored in the particular memory cell and the parity value to obtain an updated parity value; and

storing the updated parity value in the another memory cell.

7. The method of claim 6, further comprising, in response to the updated data being written to the particular memory cell, including an effect of the updated data on the updated parity value by:

performing an XOR operation on the updated data and the updated parity value to obtain a newly updated parity value; and

storing the newly updated parity value in the another memory cell.

8. The method of claim 1, further comprising delaying writes to the respective number of memory cells during a compute transaction until the compute transaction has completed.

9. The method of claim 1, further comprising recovering data stored in a particular memory cell of the respective number of memory cells determined to contain an error.

10. The method of claim 9, wherein recovering data stored in the particular memory cell further comprises performing additional XOR operations on data values stored in the respective number of memory cells other than the particular memory cell and the parity value.

11. The method of claim 10, wherein recovering data stored in the particular memory cell further comprises storing a result from the additional XOR operations in the particular memory cell.

12. The method of claim 9, wherein recovering data stored in the particular memory cell further comprises detecting the error during a compute transaction and recovering the data before restarting the compute transaction.

13. The method of claim 2, wherein performing XOR operations comprises performing a first XOR operation on a data value stored in a memory cell coupled to a first access line of the number of memory cells and a data value stored in a memory cell of the number of memory cells coupled to a second access line.

14. The method of claim 13, wherein performing XOR operations comprises performing a second XOR operation on a result of the first XOR operation and a data value stored in a memory cell coupled to a third access line of the number of memory cells.

15. The method of claim 14, comprising performing subsequent corresponding XOR operations on a previous result from a preceding XOR operation with a subsequent data value stored in a subsequent memory cell coupled to a subsequent access line.

16. An apparatus, comprising:

an array of memory cells comprising a plurality of sense lines each coupled to corresponding sensing circuitry and having a number of memory cells coupled thereto, wherein each of the number of memory cells are coupled to one of a respective number of access lines; and

wherein the sensing circuitry is operable to;

perform, on a sense line by sense line basis, a number of exclusive OR (XOR) operations on data values stored in the number of memory cells coupled to a particular sense line to determine parity values corresponding to the data stored in the memory cells of the respective plurality of sense lines without transferring data from the array via an input/output (I/O) line; and

store the determined parity values in additional memory cells coupled to the respective sense lines.

17. The apparatus of claim 16, wherein the apparatus includes a controller configured to provide control signals to the sensing circuitry to perform the number of XOR operations.

18. The apparatus of claim 17, wherein the sensing circuitry corresponding to the respective plurality of sense lines each comprises a sense amplifier and a compute component, and wherein the plurality of sense lines each have a corresponding complementary sense line also coupled to the corresponding sense amplifier and to the corresponding compute component.

19. The apparatus of claim 16, wherein the additional memory cells coupled to the respective sense lines are coupled to a same access line.

20. The apparatus of claim 16, wherein the sensing circuitry is operated to:

perform a first AND operation on the data values;

perform an invert operation on the data values;

perform an OR operation on the data values; and

perform a second AND operation on a result from the first AND operation and a result from the OR operation.

21. An apparatus, comprising:

an array storing data in each of a number of memory cells coupled to a sense line;

sensing circuitry coupled to the sense line and operable to;

perform an XOR operation on a data value stored in a first memory cell and a data value stored in a second memory cell of the number of memory cells resulting in a first resultant value without enabling a decode line corresponding to the sensing circuitry; and

perform an XOR operation on the first resultant value and a data value stored in a third memory cell of the number of memory cells resulting in a second resultant value without enabling the decode line.

22. The apparatus of claim 21, wherein the sensing circuitry is operable to perform a number of subsequent XOR operations on resultant values from prior XOR operations and data values stored in remaining memory cells of the number of memory cells without enabling the decode line.

23. The apparatus of claim 21, wherein the sensing circuitry is operable to repeat performance of XOR operations until a respective XOR operation has been performed on each of the number of memory cells coupled to the sense line;

and wherein an XOR output value from the XOR operations is a parity value corresponding to the data values stored in the number of memory cells.

24. The apparatus of claim 21, wherein the apparatus comprises a controller configured to cause a rollback to a prior state of the data values stored in the number of memory cells when an error is detected.

25. An apparatus, comprising:

an array of memory cells storing data in each of a number of memory cells coupled to a sense line;

sensing circuitry coupled to the array and operable to;

perform an XOR operation on the data stored in each of the number of memory cells without activating a decode signal, wherein the XOR operation includes;

performing a NAND operation on data values stored in a first memory cell and a second memory cell coupled to the sense line;

performing an OR operation on the data values; and

performing an AND operation on a result of the NAND operation and a result of the OR operation;

determine a parity value corresponding to the data based on a result of the AND operation; and

store the determined first parity value in an additional memory cell coupled to the sense line.

26. The apparatus of claim 25, wherein the NAND operation performed on the data values stored in the first memory cell and the second memory cell comprises:

loading a compute component coupled to the sense line with the data value stored in the first memory cell; and

enabling an access line to which the second memory cell is coupled and a control line to which a pass transistor is coupled.

27. The apparatus of claim 25, wherein the sensing circuitry is operable to invert an output value resulting from enabling the access line to which the second memory cell is coupled and the particular control signal to which the pass transistor is coupled.

28. The apparatus of claim 25, wherein the OR operation performed on the data values stored in the first memory cell and the second memory cell comprises:

loading a compute component coupled to the sense line with the data value stored in the first memory cell; and

enabling an access line to which the second memory cell is coupled and a control signal line to which an additional pass transistor is coupled.

29. The apparatus of claim 28, wherein loading the compute component comprises:

enabling an access line to which the first memory cell is coupled; and

enabling the control signal line to which the pass transistor is coupled and the control signal line to which the additional pass transistor is coupled.

30. The apparatus of claim 25, wherein the sense line is one sense line of a pair of complementary sense lines and the one sense line of the pair of complementary sense lines is coupled to the pass transistor and another sense line of the pair of complementary sense lines is coupled to the additional pass transistor.

31. That apparatus of claim 27, wherein the output value is stored in a third memory cell coupled to the sense line.

32. The apparatus of claim 31, wherein the AND operation comprises:

enabling an access line to which the third memory cell storing the output value is coupled; and

activating the control signal to which the pass transistor is coupled.

33. The apparatus of claim 32, wherein the result of the AND operation is written to a fourth memory cell by enabling an access line to which the fourth memory cell is coupled and copies the data value stored in the compute component to the fourth memory cell.

34. A method, comprising:

determining, using sensing circuitry coupled to a pair of complementary sense lines of an array of memory cells, a parity value protecting data stored in a number of memory cells coupled to a first sense line of the pair without transferring the data from the array using an input/output line, wherein determining the parity value comprises;

performing an AND operation on;

a resultant value of a NAND operation performed on a first data value stored in a first memory cell coupled to the first sense line and a second data value stored in a second memory cell coupled to the first sense line; and

a resultant value of an OR operation performed on the first data value and the second data value;

wherein performing the NAND operation includes;

loading a compute component of the sensing circuitry with the first data value; and

enabling an access line to which the second memory cell is coupled and a first pass transistor which results in a data value corresponding to an AND operation performed on the first and second data values being stored in the compute component, wherein the first pass transistor has a first source/drain region coupled to the first sense line;

inverting the data value stored in the compute component, the inverted data value being the resultant value of the NAND operation;

writing the resultant value of the NAND operation to a third memory cell coupled to the first sense line;

wherein performing the OR operation includes;

loading the compute component with the first data value; and

enabling the access line to which the second memory cell is coupled and a second pass transistor having a first source/drain region coupled to a second sense line of the pair of complementary sense lines such that the resultant value of the OR operation is stored in the compute component; and

wherein performing the AND operation on the resultant value of the NAND operation and the resultant value of the OR operation includes;

enabling an access line to which the third memory cell storing the resultant value of the NAND operation is coupled; and

enabling the first pass transistor which results in a resultant value of the AND operation performed on the NAND resultant value and the OR resultant value being stored in the compute component, wherein the resultant value is a parity value corresponding to the first and second data values.

35. The method of claim 34, wherein loading the compute component with the first data value comprises transferring the first data value from the first memory cell to the compute component by enabling an access line to which the first memory cell is coupled along with enabling the first and the second pass transistors.

36. The method of claim 34, wherein inverting the data value stored in the compute component comprises enabling an invert transistor coupled to a cross coupled latch of the compute component.

37. The method of claim 34, wherein performing the AND operation on the resultant value of the NAND operation and the resultant value of the OR operation comprises a first XOR performed on the first and second data values, and wherein determining the parity value protecting the data stored in the number of memory cells includes performing a second XOR operation on a third data value stored in a memory cell coupled to the first sense line and a result of the first XOR operation performed on the first and second data values.

38. The method of claim 37, including writing the parity value to a parity memory cell coupled to the first sense line, wherein the parity memory cell is a different memory cell than the number of memory cells.

39. The method of claim 37, wherein determining the parity value includes subsequently performing, for each additional memory cell storing a data value to be protected by the parity value, an XOR operation on the respective data value and the resultant value of an XOR operation previously performed on protected data values.

40. The method of claim 39, wherein determining the parity value includes repeating the XOR operations until the data values stored in each memory cell of the number of memory cells to be protected by the parity value has had an XOR operation performed thereon.