APPARATUSES AND METHODS FOR PARITY DETERMINATION USING SENSING CIRCUITRY
First Claim
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1. A method, comprising:
- protecting a number of data values stored in a respective number of memory cells coupled to a sense line of an array via a parity value corresponding to the number of data values that is determined without transferring data from the array via an input/output (I/O) line; and
storing the parity value in another memory cell coupled to the sense line.
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Abstract
The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
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Citations
40 Claims
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1. A method, comprising:
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protecting a number of data values stored in a respective number of memory cells coupled to a sense line of an array via a parity value corresponding to the number of data values that is determined without transferring data from the array via an input/output (I/O) line; and storing the parity value in another memory cell coupled to the sense line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An apparatus, comprising:
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an array of memory cells comprising a plurality of sense lines each coupled to corresponding sensing circuitry and having a number of memory cells coupled thereto, wherein each of the number of memory cells are coupled to one of a respective number of access lines; and wherein the sensing circuitry is operable to; perform, on a sense line by sense line basis, a number of exclusive OR (XOR) operations on data values stored in the number of memory cells coupled to a particular sense line to determine parity values corresponding to the data stored in the memory cells of the respective plurality of sense lines without transferring data from the array via an input/output (I/O) line; and store the determined parity values in additional memory cells coupled to the respective sense lines. - View Dependent Claims (17, 18, 19, 20)
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21. An apparatus, comprising:
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an array storing data in each of a number of memory cells coupled to a sense line; sensing circuitry coupled to the sense line and operable to; perform an XOR operation on a data value stored in a first memory cell and a data value stored in a second memory cell of the number of memory cells resulting in a first resultant value without enabling a decode line corresponding to the sensing circuitry; and perform an XOR operation on the first resultant value and a data value stored in a third memory cell of the number of memory cells resulting in a second resultant value without enabling the decode line. - View Dependent Claims (22, 23, 24)
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25. An apparatus, comprising:
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an array of memory cells storing data in each of a number of memory cells coupled to a sense line; sensing circuitry coupled to the array and operable to; perform an XOR operation on the data stored in each of the number of memory cells without activating a decode signal, wherein the XOR operation includes; performing a NAND operation on data values stored in a first memory cell and a second memory cell coupled to the sense line; performing an OR operation on the data values; and performing an AND operation on a result of the NAND operation and a result of the OR operation; determine a parity value corresponding to the data based on a result of the AND operation; and store the determined first parity value in an additional memory cell coupled to the sense line. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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34. A method, comprising:
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determining, using sensing circuitry coupled to a pair of complementary sense lines of an array of memory cells, a parity value protecting data stored in a number of memory cells coupled to a first sense line of the pair without transferring the data from the array using an input/output line, wherein determining the parity value comprises; performing an AND operation on;
a resultant value of a NAND operation performed on a first data value stored in a first memory cell coupled to the first sense line and a second data value stored in a second memory cell coupled to the first sense line; and
a resultant value of an OR operation performed on the first data value and the second data value;wherein performing the NAND operation includes; loading a compute component of the sensing circuitry with the first data value; and enabling an access line to which the second memory cell is coupled and a first pass transistor which results in a data value corresponding to an AND operation performed on the first and second data values being stored in the compute component, wherein the first pass transistor has a first source/drain region coupled to the first sense line; inverting the data value stored in the compute component, the inverted data value being the resultant value of the NAND operation; writing the resultant value of the NAND operation to a third memory cell coupled to the first sense line; wherein performing the OR operation includes; loading the compute component with the first data value; and enabling the access line to which the second memory cell is coupled and a second pass transistor having a first source/drain region coupled to a second sense line of the pair of complementary sense lines such that the resultant value of the OR operation is stored in the compute component; and wherein performing the AND operation on the resultant value of the NAND operation and the resultant value of the OR operation includes; enabling an access line to which the third memory cell storing the resultant value of the NAND operation is coupled; and enabling the first pass transistor which results in a resultant value of the AND operation performed on the NAND resultant value and the OR resultant value being stored in the compute component, wherein the resultant value is a parity value corresponding to the first and second data values. - View Dependent Claims (35, 36, 37, 38, 39, 40)
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Specification