APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

• US 20150357008A1
• Filed: 05/28/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Murphy, Richard C.
• Granted Patent: US 10,074,407 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a compute component. The sensing circuitry is configured to invert a data value in the compute component.

Claims

1. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array, the sensing circuitry including a compute component and the sensing circuitry being configured to invert a data value in the compute component.

2. The apparatus of claim 1, wherein the compute component comprises an accumulator.

3. The apparatus of claim 2, wherein the accumulator comprises a latch.

4. The apparatus of claim 3, wherein the latch comprises a first pair of transistors and a second pair of transistors formed on pitch with memory cells of the array.

5. The apparatus of claim 1, wherein the sensing circuitry further comprises a sense amplifier coupled to the compute component, and wherein the apparatus is further configured to store the inverted data value in the sense amplifier.

6. The apparatus of claim 5, wherein the apparatus is further configured to store the inverted data value in the sense amplifier while the array is isolated from the sensing circuitry.

7. The apparatus of claim 5, wherein the sense amplifier comprises a latch.

8. The apparatus of claim 1, wherein the array of memory cells is coupled to the sensing circuitry by a data line, the sensing circuitry being further configured to:

sense the data value from a memory cell coupled to the data line;

accumulate the data value in an accumulator of the compute component without performing a data line address access; and

invert the data value in the compute component after the data value is accumulated in the accumulator.

9. The apparatus of claim 1, wherein the sensing circuitry is coupled to the array through an isolation device.

10. The apparatus of claim 9, wherein the sensing circuitry is coupled to a second array through the isolation device, the isolation device being configured such that at most one of the array and the second array are connected to the sensing circuitry at once.

11. The apparatus of claim 9, wherein the isolation device is further configured such that the array and the second array can both be simultaneously disconnected from the sensing circuitry.

12. The apparatus of claim 1, wherein the sensing circuitry further comprises:

a sense amplifier coupled to the compute component that includes a latch and an isolation device, wherein the sense amplifier is coupled to the array through the isolation device.

13. A method for performing an invert operation, comprising:

storing a data value in a compute component coupled to a sense amplifier; and

inverting the data value in the compute component without activating an access line of a memory array coupled to the sense amplifier.

14. The method of claim 13, wherein inverting the data value in the compute component is accomplished without performing an address access of a data line of the memory array.

15. The method of claim 13, further comprising storing the inverted data value in the compute component.

16. The method of claim 13, wherein the non-inverted data value is retained in the sense amplifier while the data value is inverted in the compute component.

17. The method of claim 13, wherein the non-inverted data value is retained in the compute component while the data value is inverted in the compute component.

18. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array of memory cells via data lines, the sensing circuitry including a sense amplifier coupled to a compute component, the sensing circuitry configured to;

load, to the sense amplifier coupled to one of the data lines, a data value;

store the data value in the compute component coupled to the sense amplifier; and

invert the data value in the compute component without performing an address access of the array.

19. The apparatus of claim 18, wherein the sensing circuitry is further configured to invert the data value in the compute component without activating an I/O line coupled to the sense amplifier.

20. The apparatus of claim 18, wherein the sensing circuitry is further configured to invert the data value in the compute component and simultaneously retain the non-inverted data value in the compute component.

21. The apparatus of claim 18, wherein the sensing circuitry is further configured to:

store a second data value from a second array of memory cells in the compute component; and

invert the second data value in the compute component.

22. A method for performing an invert operation, comprising:

storing a data value in a compute component coupled to a sense amplifier;

inverting the data value to an inverted data value in the compute component; and

storing the inverted data value in the sense amplifier.

23. The method of claim 22, further comprising operating a number of isolation transistors to couple the sense amplifier to a data line of a first memory array and to isolate the sense amplifier from a data line of a second memory array prior to inverting the data value to the inverted data value, wherein inverting the data value in the compute component inverts the data value on the data line of the first memory array.

24. The method of claim 22, further comprising operating a number of isolation transistors to isolate the sense amplifier from a data line of a first memory array and a data line of a second memory array prior to inverting the data value, wherein inverting the data value in the compute component does not invert the data value on the data lines of the memory arrays.

25. The method of claim 22, further comprising storing the inverted data value in the compute component.

26. The method of claim 22, wherein inverting the data value is accomplished without amplifying a data line coupled to the compute component through an isolation device.

27. The method of claim 26, wherein the data line is a complimentary pair of data lines, and wherein inverting the data value is accomplished without amplification of the complimentary pair of data lines.

28. The method of claim 22, wherein the data value is inverted and the inverted data value is stored in the sense amplifier without activating an access line coupled to memory cells in a memory array coupled to the sense amplifier.

29. The method of claim 28, further comprising storing the inverted data value in the compute component, wherein the inverted data value is also stored in the compute component without activating the access line.