RESISTIVE CHANGE MEMORY

• US 20150357016A1
• Filed: 08/21/2015
• Published: 12/10/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: INOKUCHI, Tomoaki, ISHIKAWA, Mizue, SUGIYAMA, Hideyuki, SAITO, Yoshiaki, TANAMOTO, Tetsufumi
• Granted Patent: US 9,520,171 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.

Claims

1. A resistive change memory comprising:

a memory cell including a resistive change element and a semiconductor element, the resistive change element comprising a first terminal and a second terminal, the semiconductor element comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and

a read unit configured to perform a read operation by applying a first read voltage between the first terminal of the resistive change element and the second semiconductor layer of the semiconductor element, and then applying a second read voltage that is lower than the first read voltage between the first terminal of the resistive change element and the second semiconductor layer of the semiconductor element.

2. The memory according to claim 1, wherein the resistive change element is a magnetoresistive element including a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer.

3. The memory according to claim 1, wherein the semiconductor element is a vertical semiconductor element, and wherein the resistive change memory further comprises a gate electrode disposed on at least a part of a side surface of the semiconductor element, and a gate insulating film disposed between the gate electrode and the part of the side surface of the semiconductor element.

4. The memory according to claim 1, wherein the semiconductor element is a lateral semiconductor element, and wherein the resistive change memory further comprises a gate electrode disposed on at least a part of a top face of the semiconductor element, and a gate insulating film disposed between the gate electrode and the part of the top face of the semiconductor element.

5. The memory according to claim 1, wherein the memory cell further includes a selection transistor connected to the resistive change element or the semiconductor element.

6. The memory according to claim 1, wherein a recombination center of an electron and a hole is located at an interface between the first semiconductor layer and the third semiconductor layer of the semiconductor element.

7. The memory according to claim 1, wherein the semiconductor element is a two-terminal element.

8. The memory according to claim 1, wherein the third semiconductor layer of the semiconductor element has a terminal to extract carriers.

9. A resistive change memory comprising:

a first ferromagnetic layer and a second ferromagnetic layer;

a semiconductor element disposed between the first ferromagnetic layer and the second ferromagnetic layer, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the first ferromagnetic layer, and the second semiconductor layer being connected to the second ferromagnetic layer; and

a read unit configured to perform a read operation by applying a first read voltage between the first ferromagnetic layer and the second ferromagnetic layer, and then applying a second read voltage that is lower than the first read voltage between the first ferromagnetic layer and the second ferromagnetic layer,

a magnetization direction of one of the first ferromagnetic layer and the second ferromagnetic layer being switchable, and a magnetization direction of the other being fixed.

10. The memory according to claim 9, wherein a recombination center of an electron and a hole is disposed at an interface between the first semiconductor layer and the third semiconductor layer of the semiconductor element.

11. The memory according to claim 9, wherein the semiconductor element is a two-terminal element.

12. The memory according to claim 9, wherein the third semiconductor layer of the semiconductor element has a terminal to extract carriers.