COMPARISON OPERATIONS IN MEMORY

• US 20150357019A1
• Filed: 05/18/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wheeler, Kyle B., Manning, Troy A., Murphy, Richard C.
• Granted Patent: US 9,496,023 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating

Abstract

One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Claims

1. A method for comparing values comprising:

performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array;

wherein the comparison operation compares the first value to the second value; and

storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

2. The method of claim 1, further comprising storing the logical representation of the first value as a bit-vector in the first portion of the number of memory cells coupled to the sense line wherein each memory cell in the first portion of the number of memory cells stores a respective bit from the bit-vector.

3. The method of claim 1, further comprising storing the logical representation of the second value as a bit-vector in the second portion of the number of memory cells coupled to the sense line wherein each memory cell in the second portion of the number of memory cells stores a respective bit from the bit-vector.

4. The method of claim 1, wherein storing the logical representation of the result of the comparison operation comprises:

storing the logical representation of the result of the comparison operation as a bit-vector in the third portion of the number of memory cells coupled to the sense line wherein each memory cell in the third portion of the number of memory cells stores a respective bit from the bit-vector.

5. The method of claim 4, wherein the bit-vector in the third portion of the number of memory cells comprises at least a two bit-vector.

6. The method of claim 1, wherein the comparison operation determines whether the first value is greater than the second value.

7. The method of claim 1, wherein the comparison operation determines whether the second value is greater than the first value.

8. The method of claim 1, wherein the comparison operation determines whether the first value is equal to the second value.

9. The method of claim 1, wherein the comparison operation includes clearing a compute component and the third number of memory cells that store the logical representation of the result of the comparison operation.

10. The method of claim 1, wherein the comparison operation includes:

determining whether bits that are stored in the first portion of the number of memory cells are equal to bits that are stored in the second portion of the number of memory cells;

wherein corresponding bits from the first portion of the number of memory cells are compared to corresponding bits from the second portion of the number of memory cells.

11. The method of claim 10, wherein determining whether bits that are stored in the first portion of the number of memory cells are equal to bits that are stored in the second portion of the number of memory cells comprises:

determining whether bits with a first index from the first value and the second value are equal before determining whether bits with a second index are equal;

wherein the first index is a more significant index than a second index.

12. An apparatus comprising:

a first address space of a memory array comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space can store a first value;

a second address space of the memory array comprising a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space can store a second value;

a third address space of the memory array comprising a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space can store a result of a comparison operation; and

sensing circuitry configured to;

receive the first value and the second value;

compare the first value with the second value; and

store the result of the comparison operation in the third address space.

13. The apparatus of claim 12, wherein the sensing circuitry being configured to compare the first value with the second value comprises the sensing circuitry being configured to:

determine, from a most significant bit to a least significant bit, whether a bit from a logical representation of the first value is equal to a corresponding bit from a logical representation of the second value.

14. The apparatus of claim 13, wherein the sensing circuitry being configured to compare the first value with the second value comprises the sensing circuitry being further configured to:

if the bit from the logical representation of the first value is equal to the corresponding bit from the logical representation of the second value and if all previous bits from the logical representation of the first value are equal to all corresponding bits from the logical representation of the second value;

store a bit in the third address space that indicates that the first value is equal to the second value.

15. The apparatus of claim 13, wherein the sensing circuitry being configured to compare the first value with the second value comprises the sensing circuitry being further configured to:

if the bit from the logical representation of the first value is not equal to the corresponding bit from the logical representation of the second value;

determine whether the bit from the logical representation of the first value is greater than the corresponding bit from the logical representation of the second value.

16. The apparatus of claim 15, wherein the sensing circuitry being configured to compare the first value with the second value comprises the sensing circuitry being further configured to:

if the bit from the logical representation of the first value is greater than the corresponding bit from the logical representation of the second value;

store a bit in the third address space that indicates that the first value is greater than the second value.

17. The apparatus of claim 15, wherein the sensing circuitry being configured to compare the first value with the second value comprises the sensing circuitry being further configured to:

if the corresponding bit from the logical representation of the second value is greater than the bit from the logical representation of the first value;

store a bit in the third address space that indicates that the second value is greater than the first value.

18. A method for performing a number of comparison operations comprising:

comparing a number of first values stored in a number of first portions of memory cells coupled to a number of sense lines of a memory array to a number of second values stored in a number of second portions of the memory cells coupled to the number of sense lines of the memory array using a number of compute components that are coupled to the number of sense lines of the memory array;

storing a number of results of a number of comparison operations in a number of third portions of the memory cells coupled to the number of sense lines of the memory array; and

wherein a number of computations used to perform the number of comparison operations is the same as a number of computations used to perform any one of the number of comparison operations.

19. The method of claim 18, wherein each of the number of first portions of the memory cells is coupled to a different sense line of the number of sense lines.

20. The method of claim 19, wherein each of the number of second portions of the memory cells is coupled to a different sense line of the number of sense lines.

21. The method of claim 20, wherein each of the number of comparison operations comprises a respective first value from the number of first values being compared to a respective second value from the number of second values wherein the first value and the second value of a respective comparison operation of the number of comparison operations are stored in memory cells coupled to the same sense line of the number of sense lines.

22. The method of claim 21, wherein comparing the number of first values to the number of second values comprises:

performing a first number of exclusive disjunction (XOR) operations using a number of next most significant bits from each of the number of first values and a corresponding number of next most significant bits stored in the number of second values as input.

23. The method of claim 22, wherein comparing the number of first values to the number of second values further comprises:

performing a second number of XOR operations using a number of results of the first number of XOR operations and a number of bits stored in a number of fourth portions of the memory cells coupled to the number of sense lines of the memory array as input;

wherein the number of fourth portions of the memory cells are used to store a logical representation of a number of first temporary values that identify whether it has been determined that the number of first values are not equal to the number of second values.

24. The method of claim 23, wherein comparing the number of first values to the number of second values further comprises:

storing a number of results of the second number of XOR operations in a number of fifth portions of the memory cells coupled to the number of sense lines of the memory array;

wherein the number of fifth portions of the memory cells are used to store a logical representation of a number of second temporary values that identify whether the number of next most significant bits from each of the number of first values are not equal to the corresponding number of next most significant bits from each of the number of second values.

25. The method of claim 24, wherein comparing the number of first values to the number of second values further comprises:

performing a first number of disjunction (OR) operations using a number of bits stored in the number of fifth portions of the memory cells coupled to the number of sense lines of the memory array and the number of bits stored in the number of fourth portions of the memory cells coupled to the number of sense lines of the memory array as input;

storing a number of results of the first number of OR operations in the number of fourth portions of the memory cells to update the number of first temporary values.

26. The method of claim 25, wherein comparing the number of first values to the number of second values further comprises:

performing a first number of conjunction (AND) operations using the number of next most significant bits from the number of first values and the bits stored in the number of fifth portions of the memory cells as input to determine whether the number of first values are greater than the number of second values

27. The method of claim 26, wherein comparing the number of first values to the number of second values further comprises:

performing a second number of OR operations using a number of results of the first number of AND operations and a number of bits stored in the number of third portions of the memory cells as input; and

storing a number of results of the second number of OR operations in the number of third portions of the memory cells.

28. The method of claim 27, wherein comparing the number of first values to the number of second values further comprises:

performing a second number of AND operations using the number of next most significant bits from the number of second values and the bits stored in the number of fifth portions of the memory cells as input to determine whether the number of second values are greater than the number of first values.

29. The method of claim 28, wherein comparing the number of first values to the number of second values further comprises:

performing a third number of OR operations using a number of results of the second number of AND operations and another number of bits stored in the number of third portions of the memory cells; and

storing a number of results of the third number of OR operations in the number of third portions of the memory cells.

30. The method of claim 29, wherein comparing the number of first values to the number of second values further comprises:

if storing the number of results of the third number of OR operations in the number of third portions of the memory cells comprises the number of compute components latching a bit that indicates that all of the number of first values are equal to the number of second values;

ending the execution of the number of comparison operations.