APPARATUSES AND METHODS FOR PERFORMING AN EXCLUSIVE OR OPERATION USING SENSING CIRCUITRY
First Claim
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1. A method, comprising:
- determining, using sensing circuitry coupled to a pair of complementary sense lines of an array of memory cells, an exclusive OR (XOR) value of data stored in a number of memory cells coupled to a first sense line of the pair without transferring the data from the array using an input/output line, wherein determining the XOR value comprises;
performing an AND operation on;
a resultant value of a NAND operation performed on a first data value stored in a first memory cell coupled to the first sense line and a second data value stored in a second memory cell coupled to the first sense line; and
a resultant value of an OR operation performed on the first data value and the second data value.
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Abstract
The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
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Citations
32 Claims
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1. A method, comprising:
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determining, using sensing circuitry coupled to a pair of complementary sense lines of an array of memory cells, an exclusive OR (XOR) value of data stored in a number of memory cells coupled to a first sense line of the pair without transferring the data from the array using an input/output line, wherein determining the XOR value comprises; performing an AND operation on; a resultant value of a NAND operation performed on a first data value stored in a first memory cell coupled to the first sense line and a second data value stored in a second memory cell coupled to the first sense line; and a resultant value of an OR operation performed on the first data value and the second data value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus, comprising:
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an array of memory cells storing data in a group of memory cells coupled to a sense line; sensing circuitry coupled to the array and configured to perform an XOR operation on the data without transferring data out of the array via an input/output line, wherein the XOR operation includes; a NAND operation performed on a data value stored in a first memory cell coupled to a first access line and a data value stored in a second memory cell coupled to a second access line, wherein a resultant value of the NAND operation is stored in a third memory cell coupled to a third access line; an OR performed operation on the data values stored in the first and second memory cells; and an AND operation performed on the resultant value of the NAND operation and a resultant value of the OR operation. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An apparatus, comprising:
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an array of memory cells comprising; a plurality of sense lines coupled to a number of memory cells; and a plurality of access lines coupled to the number of memory cells; and sensing circuitry coupled to the array and configured to perform a number of exclusive OR (XOR) operations, on a sense line by sense line basis, on data values stored in each of the number of memory cells coupled to the plurality of sense lines without transferring data from the array via an input/output (I/O) line. - View Dependent Claims (20, 21, 22)
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23. A method, comprising:
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performing XOR operations on data values stored in memory cells coupled to a number of access lines and a number of sense lines using sensing circuitry coupled to each of the number of sense lines, wherein the XOR operations are performed on a sense line by sense line basis on data values stored in the memory cells coupled to each of the sensing circuitry in parallel, and performing the XOR operations on the sense line by sense line basis includes; performing a number of NAND operations on data values stored in a number of memory cells coupled to access lines; storing results of the number of NAND operations in corresponding memory cells coupled to an access line and coupled to each of the corresponding sensing circuitry; performing a number of OR operations on the data values stored in the number of memory cells; and performing a number of AND operations on the results of each of the corresponding number of NAND operations and results of each of the corresponding number of OR operations. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification