PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

• US 20150357021A1
• Filed: 05/20/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hush, Glen E.
• Granted Patent: US 9,711,206 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.

Claims

1. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array of memory cells, the sensing circuitry comprising;

a primary latch coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines; and

a secondary latch selectively coupled to the primary latch,

wherein the primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch,

wherein the primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.

2. The apparatus of claim 1, wherein the sensing circuitry comprises a sense amplifier and a compute component, the sense amplifier including the primary latch and the compute component including the secondary latch.

3. The apparatus of claim 1, wherein the primary latch and secondary latch are configured to shift a data value from the pair of adjacent complementary sense lines without charging or discharging the array of memory cells.

4. The apparatus of claim 1, wherein the primary latch is selectively coupled to the pair of adjacent complementary sense lines through a pair of transistors, each of the transistors having a gate coupled to a respective control signal line providing a control signal of V_DD to operate the pair of transistors.

5. The apparatus of claim 1, wherein the sensing circuitry is configured to:

connect complementary nodes of the secondary latch to the pair of complementary sense lines;

provide a complementary data value from the secondary latch to the pair of complementary sense lines; and

sense the complementary data value from the pair of complementary sense lines to the primary latch.

6. The apparatus of claim 1, wherein the sensing circuitry is configured to receive the data value or a complement of the data value into the secondary latch.

7. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array of memory cells via a pair of complementary sense lines,

wherein the sensing circuitry comprises;

a sense amplifier coupled to the pair of complementary sense lines; and

a compute component coupled to the sense amplifier, and

wherein the sensing circuitry is configured have a result of a logical function initially stored in the sense amplifier.

8. The apparatus of claim 7, wherein the sense amplifier includes:

a cross coupled latch coupled to the pair of complementary sense lines; and

equilibrate circuitry configured to equilibrate the pair of complementary sense lines.

9. The apparatus of claim 8, wherein the cross coupled latch comprises:

a first primary latch input coupled to a first one of the pair of complementary sense lines, and to a first source/drain region of a first transistor having a first conductivity type, and to a first source/drain region of a second transistor having a second conductivity type and to a gate of a third transistor of the first conductivity type and to a gate of a fourth transistor having the second conductivity type; and

a second primary latch input coupled to a second one of the pair of complementary sense lines and to a first source/drain region of the third transistor and to a first source/drain region of the fourth transistor and to a gate of the first transistor and to a gate of the second transistor,

wherein a second source/drain region of the first transistor is coupled to a second source/drain region of the third transistor, and a second source/drain region of the second transistor is coupled to a second source/drain region of fourth transistor.

10. The apparatus of claim 9, wherein:

the second source/drain region of the second transistor and the second source/drain region of the fourth transistor are coupled to a positive control signal;

the second source/drain region of the first transistor and the second source/drain region of the third transistor are coupled to a negative control signal; and

the positive and negative control signals are configured to activate the sense amplifier to store a data value.

11. The apparatus of claim 10 wherein the first conductivity type is an n-channel transistor and the second conductivity type is a p-channel transistor.

12. The apparatus of claim 10, wherein transistors of the sensing circuitry are formed on pitch with memory cells of the array.

13. The apparatus of claim 7, further comprising shift circuitry is configured to selectively couple the pair of complementary sense lines between the array of memory cells and the sensing circuitry.

14. The apparatus of claim 13, wherein the shift circuitry is further configured to selectively couple a pair of adjacent complementary sense lines to the sensing circuitry and isolate the array of memory cells from the sensing circuitry.

15. The apparatus of claim 7, wherein the equilibrate circuitry comprises:

a first equilibrate transistor coupled between the pair of complementary sense lines;

a first source/drain region of a second equilibrate transistor coupled to a first one of the pair of complementary sense lines;

a first source/drain region of a third equilibrate transistor coupled to a second one of the pair of complementary sense lines;

a second source/drain region of the second equilibrate transistor coupled to a second source/drain region of a third equilibrate transistor; and

a gate of the first equilibrate transistor coupled to a gate of the second equilibrate transistor and to a gate of the third equilibrate transistor.

16. The apparatus of claim 15, wherein the second source/drain region of the second equilibrate transistor and the second source/drain region of the third equilibrate transistor are coupled to an equilibration voltage supply.

17. The apparatus of claim 16, wherein the equilibration voltage supply is configured to provide a voltage magnitude of approximately one half a supply voltage provided to the array of memory cells.

18. The apparatus of claim 15, wherein the gate of the first equilibrate transistor and the gate of the second equilibrate transistor and the gate of the third equilibrate transistor are coupled to an equilibrate control signal line.

19. The apparatus of claim 7, wherein the compute component includes a cross coupled latch coupled between the pair of complementary sense lines.

20. The apparatus of claim 19, wherein the cross coupled latch comprises:

a first secondary latch input coupled to a first one of the pair of complementary sense lines and to a first source/drain region of a first transistor having a first conductivity type and to a first source/drain region of a second transistor having a second conductivity type and to a gate of a third transistor having the first conductivity type and to a fourth transistor having the second conductivity type; and

a second secondary latch input coupled to a second one of the pair of complementary sense lines and to a first source/drain region of the third transistor and to a first source/drain region of the fourth transistor and to a gate of the first transistor and to a gate of the second transistor,

wherein a second source/drain region of the first transistor is coupled to a second source/drain region of the third transistor, and a second source/drain region of the second transistor is coupled to a second source/drain region of fourth transistor.

21. The apparatus of claim 20, wherein the second source/drain region of the second transistor and the second source/drain region of the fourth transistor are coupled to a positive control signal line configured to provide a positive reference voltage, and the second source/drain region of the first transistor and the second source/drain region of the third transistor are coupled to a negative control signal line configured to provide a negative reference voltage.

22. The apparatus of claim 20, wherein the positive control signal line is coupled to a voltage supply, and the negative control signal line is coupled to ground.

23. The apparatus of claim 20, wherein the first conductivity type is an n-channel transistor and the second conductivity type is a p-channel transistors.

24. The apparatus of claim 20, wherein transistors of the compute component are formed on pitch with memory cells of the array.

25. An apparatus, comprising:

an array of memory cells;

sensing circuitry coupled to the array of memory cells via a pair of complementary sense lines; and

shift circuitry configured to selectively connect a pair of adjacent complementary sense lines to the pair of complementary sense lines,

wherein the sensing circuitry comprises;

a sense amplifier coupled to the pair of complementary sense lines; and

a compute component coupled to the sense amplifier, and

wherein the sensing circuitry is configured have a result of a logical function initially stored in the sense amplifier.

26. The apparatus of claim 25, wherein the shift circuitry is configured to selectively connect a pair of adjacent complementary sense lines to the array of memory cells and the sensing circuitry.

27. The apparatus of claim 25, wherein the shift circuitry comprises:

a first transistor coupled between a first one of the pair of adjacent complementary sense lines and a first one of the pair of complementary sense lines; and

a second transistor coupled between a second one of the pair of adjacent complementary sense lines and a second one of the pair of complementary sense lines,

wherein a gate of the first transistor and a gate of the second transistor are coupled to a shift control signal line.

28. The apparatus of claim 25, wherein the sense amplifier includes a primary latch coupled to the pair of complementary sense lines, and the compute component includes a secondary latch selectively coupled to the pair of complementary sense lines, the primary latch and the secondary latch being cross coupled latches.

29. The apparatus of claim 28, wherein compute component comprises:

a first source/drain region of a first pass transistor coupled to a first one of the pair of complementary sense lines;

a first source/drain region of a second pass transistor coupled to a second one of the pair of complementary sense lines;

a second source/drain region of the first pass transistor coupled to a first input of the secondary cross coupled latch; and

a second source/drain region of the second pass transistor coupled to a second input of the secondary cross coupled latch.

30. The apparatus of claim 29, wherein a gate of the first pass transistor is coupled to PASSD control signal line, and a gate of the second pass transistor is coupled to PASSDB control signal line, wherein the PASSD and PASSDB control signal lines are configured to communicate a control signal to load a data value into the secondary latch.

31. The apparatus of claim 29, wherein the shift circuitry includes:

a first transistor coupled between a first one of the pair of adjacent complementary sense lines and the first input of the secondary latch; and

a second transistor coupled between a second one of the pair of adjacent complementary sense lines and the second input of the secondary latch.

32. The apparatus of claim 29, wherein the shift circuitry includes:

a first transistor and a second transistor, a first source/drain region of the first transistor being coupled to a first one of the pair of adjacent complementary sense lines, and a second source/drain region of the first transistor being coupled between the second source/drain region of the first pass transistor and the first input of the secondary latch; and

a first source/drain region of the second transistor being coupled to a second one of the pair of adjacent complementary sense lines, and a second source/drain region of the second transistor being coupled between the second source/drain region of the second pass transistor and the second input of the secondary latch.

33. The apparatus of claim 29, further comprising:

a first source/drain region of a first invert transistor coupled to the first source/drain region of the first pass transistor;

a second source/drain region of a first invert transistor coupled to a first source/drain region of a first pull-down transistor;

a first source/drain region of a second invert transistor coupled to the first source/drain region of the second pass transistor;

a second source/drain region of a second invert transistor coupled to a first source/drain region of a second pull-down transistor;

a gate of the first pull-down transistor coupled to the first input of the secondary cross coupled latch;

a gate of the second pull-down transistor coupled to the second input of the secondary cross coupled latch; and

a second source/drain region of the first pull-down transistor and a second source/drain region of the second pull-down transistor coupled to a ground reference.

34. The apparatus of claim 33, wherein a gate of the first invert transistor and a gate of the second invert transistor are coupled to an invert control signal line.

35. The apparatus of claim 29, further comprising:

a first source/drain region of a first invert transistor coupled to the first source/drain region of the first pass transistor;

a second source/drain region of the first invert transistor coupled to the second input of the secondary cross coupled latch;

a first source/drain region of a second invert transistor coupled to the first source/drain region of the second pass transistor; and

a second source/drain region of the second invert transistor coupled to the second input of the secondary cross coupled latch.

36. The apparatus of claim 35, wherein a gate of the first invert transistor and a gate of the second invert transistor are coupled to an invert control signal line.

37. A method for data shifting, comprising:

writing a data value from a pair of adjacent complementary sense lines into a compute circuit without storing the data value in to a sense amplifier; and

storing the data value from the compute circuit to the sense amplifier.

38. The method of claim 37, wherein storing the data value from the compute circuit to the sense amplifier includes:

equilibrating a pair of complementary sense lines to which the sense amplifier is coupled;

communicating the data value from the compute circuit to the pair of complementary sense lines; and

storing the data value from the pair of complementary sense lines to the sense amplifier.

39. The method of claim 38, wherein storing the data value from the compute circuit to the sense amplifier further includes isolating the pair of adjacent complementary sense lines from the compute circuit before equilibrating the pair of complementary sense lines.

40. The method of claim 39, wherein communicating the data value from the compute circuit to the pair of complementary sense lines includes:

connecting the compute circuit to the pair of complementary sense lines through a pass transistor prior to sensing the data value by the sense amplifier; and

isolating the compute circuit from the pair of complementary sense lines after sensing the data value by the sense amplifier.

41. A method for data shifting, comprising:

loading a data value from a sense amplifier coupled to a pair of complementary sense lines into a compute circuit coupled to the pair of complementary sense lines; and

isolating the compute circuit from the pair of complementary sense lines;

connecting the sense amplifier to a pair of adjacent complementary sense lines; and

storing the data value from the pair of adjacent complementary sense lines to the sense amplifier.

42. The method of claim 41, wherein:

loading the data value from the sense amplifier into the compute circuit includes connecting the compute circuit to the pair of complementary sense lines through a pass transistor; and

storing the data value from the pair of adjacent complementary sense lines to the sense amplifier includes equilibrating the pair of complementary sense lines to which the sense amplifier is coupled before connecting the sense amplifier to the pair of adjacent complementary sense lines through the pass transistor.

43. The method of claim 42, further comprising isolating the sense amplifier from the pair of adjacent complementary sense lines after storing the data value to the sense amplifier.