PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

• US 20150357023A1
• Filed: 05/26/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hush, Glen E.
• Granted Patent: US 9,449,674 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry.

Claims

1. An apparatus, comprising:

an array of memory cells;

sensing circuitry coupled to the array of memory cells via a sense line, the sensing circuitry including a sense amplifier and not including an accumulator; and

a controller coupled to the array of memory cells and the sensing circuitry, the controller being configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry.

2. The apparatus of claim 1, wherein the apparatus is configured to perform logical operations using the array of memory cells for storage of operands of the logical operations.

3. The apparatus of claim 1, wherein the apparatus is configured to always sense a logic “

0”

as a result of an AND logical operation when a logic “

0”

is sensed for a first operand.

4. The apparatus of claim 1, wherein the apparatus is configured to always sense a logic “

1”

as a result of an OR logical operation when a logic “

1”

is sensed for a first operand.

5. The apparatus of claim 1, wherein the apparatus is configured to modify voltage of the sense line prior to sensing a second operand after sensing a first operand having a first data value, and to not modify voltage of the sense line prior to sensing the second operand after sensing the first operand having a second data value.

6. The apparatus of claim 5, wherein the apparatus is configured to modify voltage of the sense line to an extent that a charge of a memory cell corresponding to a second operand is not sufficient to change a data value represented by the modified voltage of the sense line prior to sensing a second operand after sensing a first operand having a first data value.

7. An apparatus, comprising:

an array of memory cells; and

a sense amplifier coupled to the array of memory cells via a sense line; and

a controller coupled to the array of memory cells, the controller being configured to;

store a first charge corresponding to a first operand of a logical operation to a plurality of memory cells coupled to a sense line;

charge an access line for the plurality of the memory cells to a voltage to which the sense line is charged plus some portion of a threshold voltage of a memory cell access device;

isolate the plurality of memory cells from the sense line;

couple a memory cell storing a charge corresponding to a second operand of the logical operation to the sense line; and

sense a voltage of the sense line as a result of the logical operation.

8. The apparatus of claim 7, wherein the controller is configured to charge the access line to within a voltage range from a threshold voltage of a memory cell access device to the threshold voltage of the memory cell access device plus an equilibration voltage.

9. The apparatus of claim 7, wherein the logical operation is an AND logical operation and wherein the controller is configured to sense the voltage of the sense line as the result of the logical operation occurs after coupling the memory cell storing the charge corresponding to the second operand to the sense line.

10. The apparatus of claim 9, wherein the controller is configured to:

store a first charge to the plurality of memory cells includes storing a first charge corresponding to a logic “

1”

; and

charge the access lines to the sense line equilibration voltage plus one-half of the memory cell access device threshold voltage does not cause a respective access device for the plurality of memory cells to turn-on.

11. The apparatus of claim 10, wherein the controller is configured to charge the access lines to the sense line equilibration voltage plus one-half of the memory cell access device threshold voltage and not modify voltage of the sense line from the equilibration voltage prior to coupling a memory cell storing a charge corresponding to a second operand to the sense line.

12. The apparatus of claim 10, wherein the controller is configured to sense the voltage of the sense line as modified from the equilibration voltage by only the charge corresponding to the second operand.

13. The apparatus of claim 7, wherein the controller is configured to:

store a first charge corresponding to a logic “

0”

; and

charge the access line to a voltage that causes a respective access device for the plurality of memory cells to turn-on.

14. The apparatus of claim 13, wherein the controller is configured to modify a voltage of the sense line to be less than the equilibration voltage prior to coupling a memory cell storing a charge corresponding to a second operand to the sense line.

15. The apparatus of claim 14, wherein the controller is configured to modify a voltage of the sense line to be less than the equilibration voltage by an amount that is more than coupling the memory cell storing the charge corresponding to the second operand can modify voltage of the sense line.

16. The apparatus of claim 7, wherein the controller is configured to sense the voltage of the sense line as modified from the equilibration voltage by a multiple of the first charge plus the charge corresponding to the second operand.

17. The apparatus of claim 7, wherein the controller is configured to sense the first charge to a sense amplifier, and wherein storing the first charge includes storing the first charge to two memory cells coupled to a same sense line.

18. The apparatus of claim 7, wherein the controller is configured to equilibrate the sense line to the equilibration voltage after isolating the plurality of memory cells from the sense line and prior to charging access lines for the plurality of the memory cells.

19. An apparatus, comprising:

an array of memory cells; and

a sense amplifier coupled to the array of memory cells via a sense line; and

a controller coupled to the array of memory cells,

wherein the controller is configured to;

simultaneously store a first charge corresponding to a first operand of a logical operation to a memory cells coupled to a plurality of access lines and coupled to a same sense line;

charge the plurality of access lines to voltage such that a data value of a first logic state will cause an access device coupled thereto to be turned-on, and such that a data value of a second logic state will cause the access device coupled thereto to be turned-off; and

couple a memory cell storing a charge corresponding to a second operand of the logical operation to the sense line after the plurality of access lines are charged without an equilibration operation after charging the plurality of access lines.

20. The apparatus of claim 19, wherein the controller is configured to charge the plurality of access lines to a sense line equilibration voltage plus a portion of a memory cell access device threshold voltage after the plurality of memory cells are isolated from the sense line.

21. A method, comprising:

storing a first charge corresponding to a first operand of a logical operation to a plurality of memory cells coupled to a sense line;

charging an access line for the plurality of the memory cells to a voltage to which the sense line is charged plus some portion of a threshold voltage of a memory cell access device;

isolating the plurality of memory cells from the sense line;

coupling a memory cell storing a charge corresponding to a second operand of the logical operation to the sense line; and

sensing a voltage of the sense line as a result of the logical operation.

22. The method of claim 21, wherein charging the access line includes charging the access line to within a voltage range from a threshold voltage of a memory cell access device to the threshold voltage of the memory cell access device plus a voltage to which the sense line is charged.

23. The method of claim 21, wherein charging the access line includes charging the access line to within a voltage range from the threshold voltage of a memory cell access device to the threshold voltage of the memory cell access device plus a sense line equilibration voltage.

24. The method of claim 21, wherein charging the access line includes charging the access line to within a voltage range from the threshold voltage of a memory cell access device to the threshold voltage of the memory cell access device plus one-half a power supply voltage.

25. The method of claim 21, wherein charging the access line includes charging the access line to a same voltage as the sense line plus one half a threshold voltage of the memory cell access device.

26. The method of claim 21, wherein charging the access line includes charging the access line to a sense line equilibration voltage plus one-half of the threshold voltage of the memory cell access device.

27. The method of claim 21, wherein the logical operation is an AND logical operation and wherein sensing the voltage of the sense line as the result of the logical operation occurs after coupling the memory cell storing the charge corresponding to the second operand to the sense line.

28. The method of claim 27, wherein:

storing a first charge to the plurality of memory cells includes storing a first charge corresponding to a logic “

1”

; and

charging the access lines to the sense line equilibration voltage plus one-half of the memory cell access device threshold voltage does not cause a respective access device for the plurality of memory cells to turn-on.

29. The method of claim 28, wherein charging the access lines to the sense line equilibration voltage plus one-half of the memory cell access device threshold voltage does not modify voltage of the sense line from the equilibration voltage prior to coupling a memory cell storing a charge corresponding to a second operand to the sense line.

30. The method of claim 28, wherein sensing the voltage of the sense line as the result of the logical operation includes sensing the voltage of the sense line as modified from the equilibration voltage by only the charge corresponding to the second operand.

31. The method of claim 21, wherein:

storing a first charge to the plurality of memory cells includes storing a first charge corresponding to a logic “

0”

; and

charging the access lines to the sense line equilibration voltage plus one-half of the memory cell access device threshold voltage causes a respective access device for the plurality of memory cells to turn-on.

32. The method of claim 31, wherein charging the access lines to the sense line equilibration voltage plus one-half of the memory cell access device threshold voltage modifies voltage of the sense line to be less than the equilibration voltage prior to coupling a memory cell storing a charge corresponding to a second operand to the sense line.

33. The method of claim 32, wherein charging the access lines to the sense line equilibration voltage plus one-half of the memory cell access device threshold voltage modifies voltage of the sense line to be less than the equilibration voltage by an amount that is more than coupling the memory cell storing the charge corresponding to the second operand can modify voltage of the sense line.

34. The method of claim 21, wherein sensing the voltage of the sense line as the result of the logical operation includes sensing the voltage of the sense line as modified from the equilibration voltage by a multiple of the first charge plus the charge corresponding to the second operand.

35. The method of claim 21, further comprising sensing the first charge to a sense amplifier, and wherein storing the first charge includes storing the first charge to two memory cells coupled to a same sense line.

36. The method of claim 21, further comprising equilibrating the sense line to the equilibration voltage after isolating the plurality of memory cells from the sense line and prior to charging access lines for the plurality of the memory cells.

37. A method, comprising:

storing a first charge corresponding to a first operand of a logical operation to memory cells including a corresponding access device coupled to a sense line and to different access lines;

charging the different access lines to within a voltage to which the sense line is charged plus some portion of a threshold voltage of a memory cell access device; and

modifying a voltage of the sense line with a second charge stored in a memory cell coupled to the sense line and to an access line other than the different access lines, the second charge corresponding to a second operand of the logical operation, the modified voltage of the sense line indicating a result of the logical operation.

38. The method of claim 37, further comprising equilibrating the sense line to an equilibrate voltage, wherein charging the different access lines to the same voltage as the sense line includes charging the different access lines to the equilibrate voltage.

39. The method of claim 37, further comprising equilibrating the sense line to an one half a supply voltage, wherein charging the different access lines to the same voltage as the sense line includes charging the different access lines to one half a supply voltage.

40. The method of claim 39, wherein the supply voltage is about 1.2V and the threshold voltage of the corresponding access device is about 0.8V.

41. The method of claim 37, further comprising isolating the memory cells coupled to the sense line and to different access lines.

42. The method of claim 37, wherein charging the different access lines includes charging the different access lines to a voltage that is insufficient to sense the second charge stored in the memory cell as a result of the logical operation when:

the logical operation is an AND operation and the first charge corresponds to a data value of “

1”

;

or

the logical operation is an OR operation and the first charge corresponds to a data value of “

0”

.

43. The method of claim 37, wherein charging the different access lines includes charging the different access lines to a voltage that is insufficient to turn-on the corresponding access device coupled to the different access lines when:

the logical operation is an AND operation and the first charge corresponds to a data value of “

1”

;

or

the logical operation is an OR operation and the first charge corresponds to a data value of “

0”

.

44. The method of claim 43, wherein modifying the voltage of the sense line with the second charge causes a voltage on the sense line to deviate from an equilibrate voltage so as to correspond to a data value corresponding to the second operand of the logical operation as the result of the logical operation.

45. The method of claim 43, wherein charging the different access lines to a voltage that is insufficient to turn-on the corresponding access device causes a voltage on the sense line to remain at an equilibrate voltage.

46. The method of claim 37, wherein charging the different access lines includes charging the different access lines to a voltage that is sufficient to turn-on the corresponding access device coupled to the different access lines when:

the logical operation is an AND operation and the first charge corresponds to a data value of “

0”

;

or

the logical operation is an OR operation and the first charge corresponds to a data value of “

1”

.

47. The method of claim 46, wherein charging the different access lines to a voltage that is sufficient to turn-on the corresponding access device causes a voltage on the sense line to deviate from an equilibrate voltage so as to correspond to a data value of “

0”

.

48. The method of claim 46, wherein charging the different access lines to a voltage that is sufficient to turn-on the corresponding access device causes a voltage on the sense line to deviate from an equilibrate voltage to an extent that modifying the voltage of the sense line with the second charge does not sufficiently change the voltage of the sense line to correspond to a different data value.

49. A method, comprising:

storing a first charge corresponding to a complement of a first operand of a logical operation to a plurality of memory cells coupled to a sense line;

charging access lines for the plurality of the memory cells to an equilibration voltage to which the sense line is charged plus some portion of a threshold voltage of a memory cell access device;

isolating the plurality of memory cells from the sense line;

coupling a memory cell storing a charge corresponding to a complement of a second operand of the logical operation to the sense line; and

sensing a voltage of the sense line as a result of the logical operation.

50. The method of claim 49, wherein charging the access lines includes charging the access lines to the equilibration voltage plus one-half of the threshold voltage of the memory cell access device.

51. The method of claim 49, wherein the logical operation is an OR logical operation and wherein sensing the voltage of the sense line as the result of the logical operation occurs after coupling the memory cell storing the charge corresponding to the complement of the second operand to the sense line.

52. The method of claim 49, further comprising sensing the first charge from a memory cell storing a complement data value to the first operand of the logical operation.

53. The method of claim 49, further comprising sensing the first charge from a complementary sense line of the same sense line.