APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY

• US 20150357024A1
• Filed: 05/29/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hush, Glen E., Manning, Troy A.
• Granted Patent: US 9,786,335 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

Claims

1. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array, and comprising a sense amplifier coupled to a pair of complementary sense lines; and

a compute component coupled to the sense amplifier and comprising a dynamic latch, and

wherein the sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

2. The apparatus of claim 1, wherein the sensing circuitry is configured to perform the logical operation without transferring data via an input/output (I/O) line.

3. The apparatus of claim 1, wherein the sensing circuitry is configured to perform the logical operation without transferring data to a control component external to the array.

4. The apparatus of claim 1, wherein the sensing circuitry is further configured to retain an input data value in the dynamic latch unchanged by performance of the logical operation.

5. The apparatus of claim 1, wherein the compute component comprises an accumulator.

6. The apparatus of claim 1, wherein the sensing circuitry is coupled to the array of memory cells through a shift circuitry intermediate in the pair of complementary sense lines.

7. The apparatus of claim 6, wherein the shift circuitry is configured to connect the sensing circuitry to one of the pair of complementary sense lines and an adjacent pair of complementary sense lines.

8. The apparatus of claim 6, wherein the shift circuitry is configured as a multiplexor capable of selecting from among at least 3 inputs to the sensing circuitry.

9. The apparatus of claim 8, wherein the shift circuitry is configured as a multiplexor capable of coupling to the sensing circuitry one of two pairs of adjacent complementary sense lines and the pair of complementary sense lines in an inverted configuration.

10. The apparatus of claim 1, wherein the compute component further comprises a static latch coupled to the dynamic latch.

11. The apparatus of claim 1, wherein, to perform an AND logical operation, the sensing circuitry is further configured to:

write a “

0”

data value to the sense amplifier unchanged when the dynamic latch reflects a “

1”

data value; and

leave a data value stored in the sense amplifier unchanged when the dynamic latch reflects a “

1”

data value.

12. The apparatus of claim 1, wherein, to perform an OR logical operation, the sensing circuitry is further configured to:

write a “

1”

data value to the sense amplifier when the dynamic latch reflects a “

1”

data value; and

leave a data value stored in the sense amplifier unchanged when the dynamic latch reflects a “

0”

data value.

13. A method, comprising:

loading a first data value to a dynamic latch of a compute component coupled to an array of memory cells via a pair of complementary sense lines;

storing a second data value to a sense amplifier coupled to the compute component via the pair of complementary sense lines;

performing a logical operation using the first data value and the second data value, and

storing a result of the logical operation initially in the sense amplifier.

14. The apparatus of claim 13, wherein the sensing circuitry is configured to perform the logical operation without transferring data via an input/output (I/O) line.

15. The apparatus of claim 13, wherein the sensing circuitry is configured to perform the logical operation without transferring data to a control component external to the array.

16. The method of claim 13, further comprising retaining the first data value in the dynamic latch unchanged by performing the logical operation.

17. The method of claim 13, further comprising storing the first data value to the sense amplifier from the array of memory cells before loading the first data value to the dynamic latch.

18. The method of claim 13, wherein performing the logical operation includes flipping a latch in the sense amplifier to invert the second data value in the sense amplifier.

19. The method of claim 18, wherein flipping the latch in the sense amplifier does not change the first data value stored to the dynamic latch.

20. The method of claim 13, further comprising pre-seeding the sense amplifier with logical operation data.

21. The method of claim 20, wherein pre-seeding the sense amplifier with logical operation data includes:

forcing the second data value stored to the sense amplifier to a “

0”

data value when the dynamic latch reflects a “

0”

data value; and

leaving the second data value stored to the sense amplifier unchanged when the dynamic latch reflects a “

1”

data value.

22. The method of claim 21, wherein pre-seeding the sense amplifier with logical operation data includes pre-seeding the sense amplifier with logical operation data prior to storing the result of the logical operation in the sense amplifier.

23. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array,

wherein the sensing circuitry comprises;

a sense amplifier coupled to a pair of complementary sense lines; and

a compute component coupled to the sense amplifier and comprising a dynamic latch, and

wherein the sensing circuitry is configured to initially store a result of a logical operation in the sense amplifier.

24. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array and comprising;

a sense amplifier coupled to a pair of complementary sense lines; and

a compute component coupled to the sense amplifier, the compute component implementing a dynamic latch; and

wherein the sensing circuitry is configured to perform a logical operation without transferring a result of the logical operation out of the sensing circuitry via an input/output (I/O) line, a result of a logical operation occurring in the sense amplifier.

25. The apparatus of claim 24, wherein the compute component comprises:

a first source/drain region of a first pass transistor directly coupled to a first one of the complementary pair of sense lines and a first source/drain region of a first load transistor;

a first source/drain region of a second pass transistor directly coupled to a second one of the complementary pair of sense lines and a first source/drain region of a second load transistor;

a second source/drain region of the first pass transistor directly coupled to a first source/drain region of a first dynamic latch transistor;

a second source/drain region of the second pass transistor directly coupled to a first source/drain region of a second dynamic latch transistor;

a second source/drain region of the first dynamic latch transistor directly coupled to a second source/drain region of the second dynamic latch transistor;

a gate of the first dynamic latch transistor directly coupled to a second source/drain region of the second load transistor;

a gate of the second dynamic latch transistor directly coupled to a second source/drain region of the first load transistor; and

a gate of the first load transistor directly coupled to a gate of the second load transistor.

26. The apparatus of claim 25, further comprising:

a gate of the first pass transistor coupled to an AND control signal input configured to provide a control signal to initiate an AND operation;

a gate of the second pass transistor coupled to an OR control signal input configured to provide a control signal to initiate an OR operation; and

the gates of the load transistors coupled to a LOAD control signal input configured to provide a control signal to initiate loading data values to the dynamic latch.

27. The apparatus of claim 25, wherein the second source/drain region of the first dynamic latch transistor and the second source/drain region of the second dynamic latch transistor are coupled to a control signal line providing either a reference voltage or an elevated reference voltage.

28. The apparatus of claim 25, wherein the second source/drain region of the first dynamic latch transistor and the second source/drain region of the second dynamic latch transistor are coupled to a control signal control signal line providing either a ground reference voltage or an elevated ground reference voltage.

29. The apparatus of claim 25, further comprising:

a first invert transistor coupled between the first source/drain region of the second load transistor and the second source/drain region of the first pass transistor; and

a second invert transistor directly coupled between the first source/drain region of the first load transistor and the second source/drain region of the second pass transistor.

30. The apparatus of claim 29, further comprising:

a gate of the first invert transistor coupled to a first invert control signal input configured to provide a control signal to initiate an OR operation involving inverted data values; and

a gate of the second invert transistor coupled to a second invert control signal input configured to provide a control signal to initiate an AND operation involving inverted data values.

31. The apparatus of claim 25, further comprising:

a first invert transistor directly coupled between the first source/drain region of the second load transistor and the second source/drain region of the first load transistor; and

a second invert transistor directly coupled between the first source/drain region of the first load transistor and the second source/drain region of the second load transistor.

32. The apparatus of claim 31, further comprising:

a gate of the first invert transistor coupled to a first invert control signal input configured to provide a control signal to initiate loading of a first inverted data value to a first node of the dynamic latch; and

a gate of the second invert transistor coupled to a second invert control signal input configured to provide a control signal to initiate loading of a second inverted data value to a second node of the dynamic latch.

33. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array and comprising;

a sense amplifier coupled to a pair of complementary sense lines; and

a compute component coupled to the sense amplifier, the compute component implementing a dynamic latch; and

wherein the sensing circuitry is operable to;

perform a logical operation on a data value stored in a first cell coupled to a first sense line of the pair of complementary sense lines and a data value stored in a second cell coupled to the first sense line,

wherein a result of a logical operation is initially stored in a latch of the sense amplifier and subsequently copied to at least one of;

a memory cell coupled to the first sense line; and

the dynamic latch.