COMPARISON OPERATIONS IN MEMORY

• US 20150357047A1
• Filed: 05/19/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tiwari, Sanjay
• Granted Patent: US 9,830,999 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/785 with decentralized control, e.g. smart memories
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

Claims

1. An apparatus comprising:

a first group of memory cells coupled to a first access line and configured to store a first element;

a second group of memory cells coupled to a second access line and configured to store a second element; and

sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

2. The apparatus of claim 1, wherein performing the number of AND operations, OR operations, INVERT operations, and SHIFT operations comprises performing the number of AND operations, OR operations, INVERT operations, and SHIFT operations without performing a sense line address access.

3. The apparatus of claim 2, further comprising performing the number of AND operations, OR operations, INVERT operations, and SHIFT operations using sensing circuitry on pitch with a number of columns of complementary sense lines corresponding to the first and second groups of memory cells.

4. The apparatus of claim 3, wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to each respective one of the number of columns.

5. The apparatus of claim 4, wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.

6. A method for comparing elements comprising:

performing, without performing a sense line address access, a comparison operation on;

a first element stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and

a second element stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array; and

wherein the comparison operation provides a result that indicates whether the first element is equal to the second element or which of the first element and the second element is greater.

7. The method of claim 6, further comprising storing the first element as a first bit-vector in the first group of memory cells, wherein each memory cell in the first group of memory cells stores a respective bit from the first bit-vector.

8. The method of claim 7, further comprising storing the second element as a second bit-vector in the second group of memory cells, wherein each memory cell in the second group of memory cells stores a respective bit from the second bit-vector.

9. The method of claim 6, wherein the first element is a first value and the second element is a second value, and wherein the result of the comparison operation indicates whether the first value is equal to the second value or which of the first value and the second value is greater.

10. An apparatus comprising:

a first group of memory cells coupled to a first access line and configured to store a first element;

a second group of memory cells coupled to a second access line and configured to store a second element; and

sensing circuitry configured to;

perform a comparison operation by comparing the first element and the second element; and

store a result of the comparison operation in a third group of memory cells without transferring data via an input/output (I/O) line.

11. The apparatus of claim 10, wherein the third group of memory cells is a same group of memory cells as at least one of:

the first group of memory cells coupled to the first access line; and

the second group of memory cells coupled to the second access line.

12. The apparatus of claim 10, wherein the third group of memory cells comprises a number of memory cells coupled to a third access line and a number of memory cells coupled to a fourth access line, wherein the third and the fourth access lines are different than the first and the second access lines.

13. The apparatus of claim 12, wherein the result of the comparison operation includes:

a first bit-vector stored in the number of memory cells of the third group that are coupled to the third access line; and

a second bit-vector stored in the number of memory cells of the third group that are coupled to the fourth access line.

14. The apparatus of claim 13, wherein, responsive to the first element being greater than the second element, the first bit-vector is a first bit pattern and the second bit-vector is a second bit pattern.

15. The apparatus of claim 14, wherein, responsive to the second element being greater than the first element, the first bit-vector is the second bit pattern and the second bit-vector is the first bit pattern.

16. The apparatus of claim 15, wherein, responsive to the first element being equal to the second element, the first bit-vector and the second bit-vector are both one of:

the first bit pattern; and

the second bit pattern.

17. The apparatus of claim 16, wherein at least one of the first bit-vector and the second bit-vector comprises only one (1) bits.

18. An apparatus comprising:

a first group of memory cells coupled to a first access line and to a number of sense lines and configured to store a first element;

a second group of memory cells coupled to a second access line and to the number of sense lines and configured to store a second element;

a third group of memory cells configured to store a result of a comparison operation performed on the first element and the second element, the third group of cells comprising;

a number of cells coupled to a third access line and to the number of sense lines; and

a number of cells coupled to a fourth access line and to the number of sense lines; and

sensing circuitry configured to perform the comparison operation and store the result of the comparison operation in the third group of memory cells without transferring data via an input/output (I/O) line.

19. The apparatus of claim 18, wherein the sensing circuitry is further configured to create a first bit-vector that identifies differences in the first element as compared to the second element.

20. The apparatus of claim 19, wherein the sensing circuitry is further configured to create a second bit-vector that identifies differences in the second element as compared to the first element.

21. The apparatus of claim 20, wherein the sensing circuitry is further configured to determine a first index that identifies a most significant one (1) bit in the first bit-vector.

22. The apparatus of claim 21, wherein the sensing circuitry is further configured to determine a second index that identifies a most significant one (1) bit in the second bit-vector.

23. The apparatus of claim 22, wherein the sensing circuitry is further configured to, responsive to a determination that the first index is greater than the second index, store a particular bit-vector in the number of memory cells coupled to the third access line and a different particular bit-vector in the number of memory cells coupled to the fourth access line to indicate that the first element is greater than the second element.

24. The apparatus of claim 22, wherein the sensing is further configured to, responsive to a determination that the second index is greater than the first index, store the different particular bit-vector in the number of memory cells coupled to the third access line and the particular bit-vector in the number of memory cells coupled to the fourth access line to indicate that the second element is greater than the first element.

25. The apparatus of claim 22, wherein the sensing circuitry is further configured to, responsive to a determination that the first and second indices are the same, store the particular bit-vector in the number of memory cells coupled to the third access line and the particular bit-vector in the number of memory cells coupled to the fourth access line to indicate that the first element is equal to the second element.

26. A method for comparing elements comprising:

performing, without performing a sense line address access, a comparison operation in memory on;

a plurality (M) of first elements stored in a first group of memory cells coupled to a first access line and to a number (C) of sense lines of a memory array; and

a plurality (M) of second elements stored in the second group of memory cells coupled to a second access line and to the C sense lines of the memory array; and

providing a comparison operation result that indicates whether the M first elements are equal to the M second elements or which of the M first elements and the M second elements are greater.

27. The method of claim 26, wherein each of the M first elements and the M second elements are comprised of N bits.

28. The method of claim 27, wherein M is equal to C divided by N.

29. The method of claim 27, wherein each of the N bits in each of the M first elements and the M second elements are associated with an index and wherein bits from corresponding elements that are associated with a same index are stored in memory cells that are coupled to a same sense line from the C sense lines.

30. The method of claim 27, further comprising, identifying a most significant bit (MSB) for the M first elements and the M second elements.

31. The method of claim 30, further comprising, identifying a least significant bit (LSB) for each of the M first elements and the M second elements.

32. The method of claim 31, wherein performing the comparison operation further comprises performing a number of iterations of operations using a mask element to isolate corresponding elements from the M first elements and the M second elements, wherein the mask element is created using the MSB for the M first elements and the M second elements.

33. The method of claim 32, wherein each iteration of operations of the number of iterations of operations further comprises determining whether an element from the M first elements is greater than a corresponding element from the M second elements.

34. The method of claim 33, wherein each iteration of operations of the number of iterations of operations further comprises determining whether an element from the M first elements is less than the corresponding element from the M second elements.

35. The method of claim 34, wherein each iteration of operations of the number of iterations of operations further comprises determining whether an element from the M first elements is equal to the corresponding element from the M second elements.

36. The method of claim 34, wherein each iteration of operations of the number of iterations of operations further comprises performing an AND operation on corresponding elements from the M first elements and the M second elements to find shared bits, and wherein a shared bit refers to a particular bit in an element from the M first elements and having a particular index being the same as a corresponding bit in an element from the M second elements and having the particular index.

37. The method of claim 36, wherein each iteration of operations of the number of iterations of operations further comprises performing an INVERT operation using a result of the AND operation to identify bits that are not shared between corresponding elements.

38. The method of claim 37, wherein each iteration of operations of the number of iterations of operations further comprises:

identifying differences in the second element as compared to the first element by performing an AND operation on a result of the INVERT operation and a first element from the corresponding elements;

identifying differences in the first element as compared to the second element by performing an AND operation on the result of the INVERT operation and the second element from the corresponding elements;

identifying a first most significant one (1) bit from a result of the AND operation using the result of the INVERT operation and a first element from the corresponding elements; and

identifying a second most significant one (1) bit from the result of the AND operation using the result of the INVERT operation and a second element from the corresponding elements;

wherein identifying the first most significant one (1) bit and the second most significant one (1) bit includes performing a plurality of AND operations, a plurality of BLOCKOR operations, and a plurality of SHIFT operations; and

wherein the first most significant one (1) bit and the second most significant one (1) bit are identified using the LSB.

39. The method of claim 38, wherein each iteration of operations of the number of iterations of the operations further comprises:

storing results of the comparison operation in a third group of memory cells coupled to a third access line and to the number of sense lines of the memory array;

wherein the result of the comparison operation is based on a comparison between the first most significant one (1) bit and the second most significant one (1) bit; and

wherein the results of the comparison operation is updated during each iteration of operations of the number of iterations of operations using an OR operation.