ROM Chip Manufacturing Structures

• US 20150357327A1
• Filed: 08/18/2015
• Published: 12/10/2015
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Granted Patent: US 9,418,991 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include first portions of first and second gate structures, respectively. The IC chip further includes a strap cell disposed between the first and second ROM cells. The strap cell includes second portions of the first and second gate structures. The first gate structure is physically separated from the second gate structure.

Claims

1. An integrated circuit (IC) chip comprising:

a first read only memory (ROM) cell comprising a first portion of a first gate structure;

a second ROM cell in a same row of a ROM array as the first ROM cell, wherein the second ROM cell comprises a first portion of a second gate structure physically separated from the first gate structure, wherein the row of the ROM array runs in a direction substantially parallel to a lengthwise direction of the first gate structure and the second gate structure; and

a strap cell disposed between the first ROM cell and the second ROM cell, wherein the strap cell comprises a second portion of the first gate structure and a second portion of the second gate structure.

2. The IC chip of claim 1, wherein the strap cell further comprises a first connection module electrically connecting the first gate structure and the second gate structure to a word line.

3. The IC chip of claim 2, wherein the first connection module comprises:

a first gate contact connected to the first gate structure; and

a second gate contact connected to the second gate structure.

4. The IC chip of claim 2, wherein the first connection module comprises an expanded gate contact, wherein a first end of the expanded gate contact is connected to the first gate structure, and wherein a second end of the expanded gate contact is connected to the second gate structure.

5. The IC chip of claim 2, wherein the first connection module comprises:

a first-level via;

a first-level metal line over the first-level via; and

a second-level via over the first-level metal line, wherein the first-level via, the first-level metal line, and the second-level via electrically connect the first gate structure and the second gate structure to the word line.

6. The IC chip of claim 1, wherein the first ROM cell comprises at least a portion of a first isolation device, wherein the second ROM cell comprises at least a portion of a second isolation device, wherein the first isolation device and the second isolation device share a third gate structure, and wherein the third gate structure extends continuously from the first ROM cell through the strap cell to the second ROM cell.

7. The IC chip of claim 6, further comprising a second connection module electrically connecting the third gate structure to a first voltage supply line.

8. The IC chip of claim 1, wherein the first ROM cell comprises:

a source region, wherein;

the first ROM cell is configured in a first logical state when the source region is electrically connected to a second voltage supply line; and

the first ROM cell is configured in a second logical state when the source region is not electrically connected to the second voltage supply line; and

a drain region electrically connected to a bit line.

9. The IC chip of claim 8, further comprising a third voltage supply line, wherein the second voltage supply line is configured in a perpendicular direction to the third voltage supply line, and wherein a via electrically connects the second voltage supply line to the third voltage supply line.

10. The IC chip of claim 1, wherein the first gate structure and the second gate structure provide gates for fin field-effect transistors (finFETs).

11. A device comprising:

a first gate structure;

a second gate structure in a same memory array row as the first gate structure, wherein the memory array row runs in a direction substantially parallel to a lengthwise dimension of the first gate structure and the second gate structure, and wherein the first gate structure and the second gate structure are substantially uniform in length and physically separated; and

a strap cell comprising first portions of the first gate structure and the second gate structure, wherein the strap cell electrically connects the first gate structure and the second gate structure to a common word line.

12. The device of claim 11, wherein the strap cell further comprises a first via physically connected to the first gate structure and a second via physically connected to the second gate structure, wherein the first via and the second via are physically separated and electrically connected to the common word line.

13. The device of claim 11, wherein the strap cell further comprises a third via physically connected to both the first gate structure and the second gate structure, wherein the third via is electrically connected to the common word line.

14. The device of claim 11, wherein a memory array comprising the memory array row and the strap cell further comprises a first memory cell and a second memory cell, wherein the strap cell is disposed between the first memory cell and the second memory cell, wherein the first memory cell comprises a second portion of the first gate structure, and wherein the second memory cell comprises a second portion of the second gate structure.

15. The device of claim 11, wherein the strap cell further comprises at least a portion of an isolation structure comprising a third gate structure, wherein the third gate structure extends continuously through the strap cell.

16. The device of claim 11, wherein the strap cell further comprises at least a portion of an isolation structure comprising a fourth gate structure and a fifth gate structure physically separated from the fourth gate structure.

17. A method comprising:

forming a first gate structure in a memory array row, wherein the memory array row runs in a direction substantially parallel to the first gate structure;

forming a second gate structure in the memory array row, wherein the second gate structure is physically separated from the first gate structure; and

electrically connecting the first gate structure and the second gate structure to a common word line using a strap cell, wherein the strap cell comprises at least a portion of both the first gate structure and the second gate structure.

18. The method of claim 17, wherein electrically connecting the first gate structure and the second gate structure to a common word line comprises:

physically connecting a first via of the strap cell to the first gate structure; and

physically connecting a second via of the strap cell to the second gate structure, wherein the first via and the second via are physically separated.

19. The method of claim 17, wherein electrically connecting the first gate structure and the second gate structure to a common word line comprises physically connecting a third via of the strap cell to both the first gate structure and the second gate structure.

20. The method of claim 17, wherein forming the first gate structure and forming the second gate structure comprises forming the first gate structure and the second gate structures to have substantially uniform lengths.