TRANSISTOR ARRAY AND MANUFACTURING METHOD THEREOF

• US 20150357374A1
• Filed: 12/12/2013
• Published: 12/10/2015
• Est. Priority Date: 01/11/2013
• Status: Active Grant

• Current Assignee: Beijing Institute of Nanoenergy and Nanosystems
• Original Assignee: Beijing Institute of Nanoenergy and Nanosystems
• Inventors: Wang, Zhonglin, Wu, Wenzhuo, Wen, Xiaonan
• Granted Patent: US 10,644,063 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01L 1/16 using properties of piezoelectric devices
• CPC Class Codes: G01L 9/08 by making use of piezoelectric devices , i.e. electric circuits therefor
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10N 30/01 Manufacture or treatment
• CPC Class Codes: H10N 30/06 Forming electrodes or interconnections, e.g. leads or terminals
• CPC Class Codes: H10N 30/077 by liquid phase deposition
• CPC Class Codes: H10N 30/302 Sensors
• CPC Class Codes: H10N 30/853 Ceramic compositions
• CPC Class Codes: H10N 30/8554 Lead zirconium titanate based
• CPC Class Codes: H10N 30/857 Macromolecular compositions
• CPC Class Codes: H10N 30/877 Conductive materials in general H01B1/00
• CPC Class Codes: H10N 30/883 Further insulation means against electrical, physical or chemical damage, e.g. protective coatings
• CPC Class Codes: H10N 39/00 Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00

Abstract

The disclosure provides a transistor array including a substrate and a plurality of transistor elements sharing the substrate. Each of the transistor elements includes: a bottom electrode disposed on the substrate and a connection wire for the bottom electrode; a piezoelectric body disposed on the bottom electrode, wherein the piezoelectric body is made of piezoelectric material; and a top electrode disposed on the piezoelectric body. The disclosure also provides a method for manufacturing a transistor array. The transistor array contains transistor elements which are two-terminal devices. Piezoelectric bodies with piezoelectric properties are provided between the top electrodes and bottom electrodes of the transistor array. The carrier transport progress of the transistor elements in the transistor array device can be effectively regulated or triggered by strains or stresses applied on the transistor elements.

Claims

1. A transistor array including a substrate and a plurality of transistor elements sharing the substrate, wherein each of the transistor elements comprising:

a bottom electrode disposed on the substrate and a connection wire for the bottom electrode;

a piezoelectric body disposed on the bottom electrode, wherein the piezoelectric body is made of piezoelectric material; and

a top electrode disposed on the piezoelectric body.

2. The transistor array of claim 1, wherein the piezoelectric body of each transistor element has a polarized orientation.

3. The transistor array of claim 2, wherein the polarized orientation of the piezoelectric body of each transistor element is substantially perpendicular to the surface of the substrate.

4. The transistor array of claim 2, wherein the polarized orientations of the piezoelectric bodies of the transistor elements in the transistor array is substantially the same.

5. The transistor array of claim 1, there further includes a flexible insulation layer between the transistor elements in the transistor array, wherein at least the top electrodes of the transistor elements are exposed on the upper surface of the flexible insulation layer.

6. The transistor array of claim 5, wherein each transistor element further includes a connection wire for the top electrode, and wherein the connection wire is configured to draw the top electrode outside the transistor array.

7. The transistor array of claim 6, wherein the transistor array further includes an encapsulation layer disposed on the flexible insulation layer and configured to encapsulate parts of the transistor elements which are exposed on the upper surface of the flexible insulation layer.

8. The transistor array of claim 1, wherein the piezoelectric body of each transistor element is nanowires, nanorods or film made of ZnO, GaN, CdS, InN, InGaN, CdTe, CdSe, ZnSnO₃, or lead zirconate titanate, or nanofibers made of poly(vinylidene fluoride) (PVDF).

9. The transistor array of claim 8, wherein the piezoelectric body of each transistor element is nanowires, nanorods or nanofibers, wherein an axial direction of the piezoelectric body is substantially perpendicular to the surface of the bottom electrode or the substrate.

10. The transistor array of claim 1, wherein a cross section area of each transistor element is 25 μ

m² or less.

11. The transistor array of claim 10, wherein a distance between the transistor elements ranges from several microns to several millimeters.

12. The transistor array of claim 1, wherein the transistor elements are cylinders, quadrangular prisms, hexagonal prisms, or irregular poles whose axial directions are substantially perpendicular to the substrate.

13. The transistor array of claim 1, wherein the piezoelectric bodies of the transistor elements are made of the same piezoelectric material.

14. The transistor array of claim 1, there includes multiple identical transistor elements.

15. The transistor array of claim 1, wherein the substrate is a flexible or rigid substrate.

16. The transistor array of claim 1, wherein the top electrode and/or the bottom electrode of each transistor element is made of one of conductive oxide, graphene, or Ag nanowire coating, or one of Au, Ag, Pt, Al, Ni, Cu, Ti, Cr, Se or alloy thereof.

20. The transistor array of claim 4, there further includes a flexible insulation layer between the transistor elements in the transistor array, wherein at least the top electrodes of the transistor elements are exposed on the upper surface of the flexible insulation layer.

17. A method for manufacturing a transistor array, including:

providing a substrate;

on the substrate, manufacturing a bottom electrode array including a plurality of bottom electrodes, and connection wires for the bottom electrodes;

on the bottom electrodes, manufacturing piezoelectric bodies forming a piezoelectric body array; and

on the piezoelectric bodies, manufacturing top electrodes forming a top electrode array.

18. The method of claim 17, wherein after manufacturing piezoelectric bodies on the bottom electrodes, the method further includes:

between the piezoelectric bodies, manufacturing a flexible insulation layer, wherein the top parts of the piezoelectric bodies are exposed outside the flexible insulation layer.

19. The method of claim 18, wherein manufacturing top electrodes on the piezoelectric bodies further includes:

on the piezoelectric bodies and the flexible insulation layer, manufacturing the top electrodes and connection wires for top electrodes, wherein the top electrodes are located on the piezoelectric bodies, and the connection wires for top electrodes are electrically connected to the top electrodes.