SEMICONDUCTOR MEMORY DEVICE

• US 20150357376A1
• Filed: 03/05/2015
• Published: 12/10/2015
• Est. Priority Date: 06/09/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Boyoung Seo
• Inventors: Seo, Boyoung, Lee, Yongkyu, Chun, Keemoon
• Granted Patent: US 9,401,385 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate.

Claims

1. A semiconductor memory device comprising:

a first bit line that is at a first height from a semiconductor substrate;

a second bit line that is at a second height from the semiconductor substrate, the second height different from the first height;

a first variable resistance memory element that is connected to the first bit line and that is at a third height from the semiconductor substrate; and

a second variable resistance memory element that is connected to the second bit line and that is substantially at the third height.

2. The semiconductor memory device of claim 1, wherein the third height of the first and second variable resistance memory elements is between the first height of the first bit line and the second height of the second bit line in a vertical view.

3. The semiconductor memory device of claim 1, wherein the first and second bit lines extend in parallel along a first direction when viewed from a plan view.

4. The semiconductor memory device of claim 3, wherein the first variable resistance memory element is at a position that is shifted from the second variable resistance memory element in a diagonal direction with respect to the first direction, when viewed from a plan view.

5. The semiconductor memory device of claim 1, wherein ones of the first and second variable resistance memory elements comprise:

a pinned magnetic layer;

a free magnetic layer; and

a tunnel barrier layer that is between the pinned magnetic layer and the free magnetic layer,

wherein the free magnetic layer of the first variable resistance memory element is adjacent the first bit line, and

wherein the pinned magnetic layer of the second variable resistance memory element is adjacent the second bit line.

6. The semiconductor memory device of claim 1, further comprising:

a selection transistor that is connected in common to the first and second variable resistance memory elements.

7. The semiconductor memory device of claim 1, further comprising:

a device isolation layer that defines an active portion in the semiconductor substrate;

a word line that intersects the active portion;

first and second dopant regions in the active portion at both sides of the word line;

a source line that is connected to the first dopant region; and

a conductive pattern that is substantially at the second height of the second bit line and electrically connected to the second dopant region,

wherein the conductive pattern is electrically connected in common to the first and second variable resistance memory elements.

8. The semiconductor memory device of claim 7, further comprising:

an interconnection pattern that is substantially at the first height as the first bit line, wherein the interconnection pattern electrically connects the conductive pattern to the second variable resistance memory element.

9. The semiconductor memory device of claim 7, wherein ones of the first and second variable resistance memory elements comprise:

a pinned magnetic layer;

a free magnetic layer; and

a tunnel barrier layer that is between the pinned magnetic layer and the free magnetic layer,

wherein the pinned magnetic layer of the first variable resistance memory element is on a top surface of the conductive pattern, and

wherein the pinned magnetic layer of the second variable resistance memory element is on a top surface of the second bit line.

10. The semiconductor memory device of claim 1, further comprising:

a source line;

a first selection transistor that is connected between the source line and the first variable resistance memory element; and

a second selection transistor that is connected between the source line and the second variable resistance memory element.

11. The semiconductor memory device of claim 1, further comprising:

a device isolation layer that defines first and second active portions in the semiconductor substrate;

a word line that intersects the first and second active portions;

first and second dopant regions in each of the first and second active portions at both sides of the word line;

a source line that is connected in common to the first dopant regions of the first and second active portions;

a conductive pattern that is substantially at the second height of the second bit line and electrically connected to the second dopant region of the first active portion; and

an interconnection pattern that is substantially at the first height of the first bit line and that electrically connects the conductive pattern to the second variable resistance memory element.

12. The semiconductor memory device of claim 11, wherein the second variable resistance memory element comprises:

a pinned magnetic layer;

a free magnetic layer; and

a tunnel barrier layer between the pinned magnetic layer and the free magnetic layer, and

wherein the pinned magnetic layer of the second variable resistance memory element is on a top surface of the second bit line.

13. The semiconductor memory device of claim 11, wherein the first variable resistance memory element is electrically connected to the second dopant region of the second active portion.

14. The semiconductor memory device of claim 11, wherein the first variable resistance memory element comprises:

a pinned magnetic layer;

a free magnetic layer; and

a tunnel barrier layer between the pinned magnetic layer and the free magnetic layer,

wherein the free magnetic layer of the first variable resistance memory element is adjacent a bottom surface of the first bit line.

15. A semiconductor memory device comprising:

first and second bit lines that extend in parallel to each other and at substantially a same height from a top surface of a semiconductor substrate;

a first variable resistance memory element that is connected to the first bit line; and

a second variable resistance memory element that is connected to the second bit line,

wherein the first variable resistance memory element and the second variable resistance memory element are at different heights from the top surface of the semiconductor substrate.

16. The semiconductor memory device of claim 15,

wherein the first variable resistance memory element comprises:

a first pinned magnetic layer;

a first tunnel barrier layer; and

a first free magnetic layer,

wherein the first pinned magnetic layer, the first tunnel barrier layer and the first free magnetic layer are sequentially stacked, and

wherein the second variable resistance memory element comprises;

a second free magnetic layer;

a second tunnel barrier layer; and

a second pinned magnetic layer,

wherein the second free magnetic layer, the second tunnel barrier layer and the second pinned magnetic layer are sequentially stacked.

17. The semiconductor memory device of claim 15, wherein the first and second bit lines extend in parallel along one direction when viewed from a plan view.

18. A semiconductor memory device comprising:

a source line;

a first bit line and a second bit line that each extend in parallel along one direction on the source line;

a first variable resistance memory element that is connected between the source line and the first bit line; and

a second variable resistance memory element that is connected between the source line and the second bit line,

wherein ones of the first and second variable resistance memory elements comprise;

a pinned magnetic layer;

a free magnetic layer; and

a tunnel barrier layer between the pinned and free magnetic layers,

wherein the free magnetic layer of the first variable resistance memory element is adjacent the first bit line, and

wherein the pinned magnetic layer of the second variable resistance memory element is adjacent the second bit line.

19. The semiconductor memory device of claim 18, wherein the first bit line and the second bit line are at different heights from a top surface of a semiconductor substrate, and

wherein the first and second variable resistance memory elements are at substantially a same height from the top surface of the semiconductor substrate.

20. The semiconductor memory device of claim 18, wherein the first bit line and the second bit line are at substantially a same height from a top surface of a semiconductor substrate, and

wherein the first variable resistance memory element and the second variable resistance memory element are at different heights from the top surface of the semiconductor substrate.

21. A semiconductor memory device comprising:

first and second bit lines that extend in parallel to each other and are spaced apart in a first direction;

a source line that is at a different height from a top surface of a semiconductor substrate than the first bit line and that is at a different height from the top surface of the semiconductor substrate than the second bit line;

a first variable resistance memory element that is connected to the first bit line and to the source line and that comprises;

a first pinned magnetic layer;

a first free magnetic layer; and

a first tunnel barrier layer between the first pinned magnetic layer and the first free magnetic layer; and

a second variable resistance memory element that is connected to the second bit line and to the source line and that comprises;

a second pinned magnetic layer;

a second free magnetic layer; and

a second tunnel barrier layer between the second pinned magnetic layer and the second free magnetic layer .

22. The semiconductor memory device according to claim 21, wherein the first bit line and the second bit line are at different heights from the top surface of a semiconductor substrate, and

wherein the first and second variable resistance memory elements are at substantially a same height from the top surface of the semiconductor substrate.

23. The semiconductor memory device according to claim 21, wherein the first bit line and the second bit line are at a same height from the top surface of a semiconductor substrate, and

wherein the first and second variable resistance memory elements are at different heights from the top surface of the semiconductor substrate.

24. The semiconductor memory device according to claim 21,

wherein the first free magnetic layer of the first variable resistance memory element is adjacent a bottom surface of the first bit line, and

wherein the second pinned magnetic layer of the second variable resistance memory element is adjacent a bottom surface of the second bit line.

25. The semiconductor memory device according to claim 21, further comprising:

a first selection transistor that is connected between the source line and the first variable resistance memory element; and

a second selection transistor that is connected between the source line and the second variable resistance memory element.

26. The semiconductor memory device according to claim 21, wherein the first variable resistance memory element is at a position that is shifted from the second variable resistance memory element in a diagonal direction with respect to the first direction, when viewed from a plan view.