SEMICONDUCTOR DEVICE WITH ISOLATING LAYER ON SIDE AND BOTTOM SURFACES

• US 20150357408A1
• Filed: 06/05/2015
• Published: 12/10/2015
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Poelzl, Martin
• Granted Patent: US 9,583,565 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0692 Surface layout

Abstract

A method for manufacturing a semiconductor device comprises includes providing a substrate with a surface, forming an isolating layer on part of the surface, and forming a first semiconductor portion and spaced therefrom a second semiconductor portion on the surface of the substrate. The isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion which face each other. The method further includes forming a first side isolation layer on the side surface of the first semiconductor portion.

Claims

1. A method for manufacturing a semiconductor device comprising:

providing a substrate with a surface;

forming an isolating layer on part of the surface;

forming a first semiconductor portion and forming a second semiconductor portion spaced therefrom on the surface of the substrate, wherein the isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion, which face each other; and

forming a first side isolation layer on the side surface of the first semiconductor portion.

2. The method of claim 1, further comprising:

forming a second side isolation layer on the side surface of the second semiconductor portion.

3. The method of claim 1, wherein the isolating layer comprises a first intermediate portion and a second intermediate portion and a part of the first semiconductor portion is formed to laterally overlap the first intermediate portion and a part of the second semiconductor portion is formed to laterally overlap the second intermediate portion.

4. The method of claim 1, further comprising forming a first top isolation layer on a surface of the first semiconductor portion opposite to the substrate, and forming a second top isolation layer on a surface of the second semiconductor portion opposite to the substrate.

5. The method of claim 4, wherein the act of forming the first top isolation layer and the second top isolation layer and/or the act of forming the first side isolation layer and the second side isolation layer are performed by an oxidation process comprising oxidizing exposed surfaces of the first semiconductor portion and the second semiconductor portion.

6. The method of claim 4, further comprising:

forming a first masking layer on the first top isolation layer opposite to the substrate or forming a second masking layer on the second top isolation layer opposite to the substrate,

wherein the first masking layer is formed on part of first top isolation layer so that a first portion of the first top isolation layer remains exposed, and the second masking layer is formed on part of the second top isolation layer so that a second portion of the second top isolation layer remains exposed.

7. The method of claim 6, further comprising:

removing an exposed portion of the isolating layer so that the first intermediate portion and the first side portion form a first L-shaped isolation, and the second intermediate portion and the second side portion form a second L-shaped isolation.

8. The method of claim 6, further comprising:

removing the first top isolation layer and the second top isolation layer or removing the first masking layer and the second masking layer.

9. The method according of claim 4, further comprising:

forming at least one of the following structures between the first and second semiconductor portions;

forming a protrusion of the substrate; and

forming a protrusion of the substrate and a third top isolating layer on the protrusion.

10. A method for manufacturing a semiconductor device, comprising:

providing a non-planar substrate with a protrusion;

forming an isolation layer such that the isolation layer covers at least partially the protrusion; and

forming a first semiconductor portion and a second semiconductor portion such that the protrusion is between the first semiconductor portion and the second semiconductor portion.

11. The method of claim 10, wherein the isolation layer comprises a first side isolating portion, a second side isolating portion and a top isolating portion, wherein the protrusion is arranged between the first side isolating portion and the second side isolating portion, and the top isolating portion connects the first side isolating portion and the second side isolating portion, the method further comprising removing the top isolating portion.

12. The method of claim 11, further comprising:

forming a first side isolating layer and a second side isolating layer at facing side surfaces of the first semiconductor portion and the second semiconductor portion.

13. The method of claim 10, further comprising:

forming, in a region between the first side isolation layer and the second side isolation layer, an isolating portion and a third semiconductor portion.

14. The method of claim 13, further comprising:

forming a first type of semiconductor element in the first semiconductor portion or in the second semiconductor portion and forming a second type of semiconductor element in the third semiconductor portion, wherein the first type of semiconductor element comprises a higher blocking voltage than the second type of semiconductor element.

15. The method of claim 10, further comprising:

at least partly thinning the substrate and performing a planarization process on a surface of the first top isolation layer or of the second top isolation layer opposite to the substrate.

16. The method of claim 10, wherein forming the first semiconductor portion and spaced therefrom the second semiconductor portion on the surface of the substrate comprises epitaxial growth of the first semiconductor portion and the second semiconductor portion.

17. A semiconductor device, comprising:

an intermediate structure;

a first semiconductor portion with a side surface;

a second semiconductor portion, wherein the first semiconductor portion and the second semiconductor portion are spaced from each other and the intermediate structure is interposed between the side surface of the first semiconductor portion and a facing side surface of the second semiconductor portion; and

a first side isolation layer on the side surface of the first semiconductor portion,

wherein the first semiconductor portion laterally overlaps a first intermediate isolation layer and the second semiconductor portion laterally overlaps a second intermediate isolation layer.

18. The semiconductor device of claim 17, further comprising:

a second side isolating layer formed on the facing side surface of the second semiconductor portion, wherein the second semiconductor portion laterally overlaps a second intermediate isolation layer,

wherein the first side isolating layer and the first intermediate isolation layer comprises a first L-shaped isolation, and

wherein the second side isolating layer and the second intermediate isolation layer comprises a second L-shaped isolation.

19. The semiconductor of claim 17, further comprising:

a third semiconductor portion between the first side isolating layer and the second side isolating layer representing the intermediate structure, and wherein

at least one of the following components in the first semiconductor portion or in the second semiconductor portion or in the third semiconductor portion comprises;

a plurality of differently doped layers;

a plurality of trenches;

a contacting structure; and

an embedded device.

20. The semiconductor device of claim 17, further comprising a third semiconductor portion between the first side isolating layer and the second side isolating layer representing the intermediate structure;

and

a back side contact arranged at a backside of a semiconductor substrate structure of the semiconductor device, wherein the semiconductor substrate structure includes at least the first semiconductor portion, and wherein the third semiconductor portion is electrically insulated from the backside contact.