SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20150357422A1
• Filed: 05/29/2015
• Published: 12/10/2015
• Est. Priority Date: 06/06/2014
• Status: Active Grant

• Current Assignee: Ancora Semiconductors Incorporated
• Original Assignee: Delta Electronics Incorporated
• Inventors: LIAO, Wen-Chia
• Granted Patent: US 10,229,978 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.

Claims

1. A semiconductor device, comprising:

a substrate;

an active layer disposed on the substrate;

a source electrode and a drain electrode disposed on or above the active layer;

a p-type doped layer disposed on the active layer and between the source electrode and the drain electrode, wherein the p-type doped layer has a first thickness;

a gate electrode disposed on the p-type doped layer;

a first passivation layer covering at least the gate electrode and the active layer; and

a field plate disposed on or above the first passivation layer and electrically connected to the source electrode, wherein the field plate comprises a field dispersion portion disposed between the gate electrode and the drain electrode, and the first passivation layer has a second thickness between the field dispersion portion and the active layer;

wherein the second thickness is smaller than the first thickness.

2. The semiconductor device of claim 1, wherein the field plate and the source electrode are integrally formed.

3. The semiconductor device of claim 2, wherein the field plate further comprises an extending portion connecting to the field dispersion portion and the source electrode, and at least a portion of the extending portion is disposed above the gate electrode.

4. The semiconductor device of claim 2, wherein the field dispersion portion has a step facing the active layer.

5. The semiconductor device of claim 1, further comprising a second passivation layer covering at least the first passivation layer and the field dispersion portion of the field plate.

6. The semiconductor device of claim 5, wherein the field plate further comprises an extending portion and a conductive element, the extending portion is electrically connected to the source electrode and is disposed on the second passivation layer, and the conductive element is electrically connected to the extending portion and the field dispersion portion.

7. The semiconductor device of claim 5, wherein the second passivation layer has a through hole to expose the field dispersion portion, and the field plate further comprises an extending portion and a conductive element, the extending portion is electrically connected to the source electrode and is disposed on the second passivation layer, and the conductive element is disposed in the through hole to be electrically connected to the extending portion and the field dispersion portion.

8. The semiconductor device of claim 1, further comprising:

an insulating layer disposed on the first passivation layer and the field dispersion portion; and

a second passivation layer deposed on the insulating layer, wherein the field plate further comprises;

an extending portion disposed on the second passivation layer; and

an interlayer portion disposed between the extending portion and the field dispersion portion and between the insulating layer and the second passivation portion.

9. The semiconductor device of claim 1, wherein the second thickness T2 satisfies 0<

T2<

100 nm.

10. The semiconductor device of claim 1, wherein the p-type doped layer is made of GaN or AlGaN doped with p-type dopants.

11. A method for manufacturing a semiconductor device, comprising:

providing a substrate;

forming an active layer on the substrate;

forming a p-type doped layer on the active layer, wherein the p-type doped layer has a first thickness;

forming a gate electrode on the p-type doped layer;

forming a passivation layer to cover the gate electrode and the active layer;

forming a source via hole, a drain via hole, and a blind hole in the passivation layer, wherein the p-type doped layer is disposed between the source via hole and the blind hole, the blind hole is disposed between the p-type doped layer and the drain via hole, a portion of the passivation layer under the blind hole has a second thickness smaller than the first thickness; and

respectively forming a source electrode, a field plate and a drain electrode in the source via hole, the blind hole, and the drain via hole.

12. The manufacturing method of claim 11, wherein the p-type doped layer is made of GaN or AlGaN doped with p-type dopants.

13. The manufacturing method of claim 11, wherein forming the blind hole comprises:

forming a step at a side of the blind hole facing the active layer.

14. A method for manufacturing a semiconductor device, comprising:

providing a substrate;

forming an active layer on the substrate;

forming a p-type doped layer on the active layer, wherein the p-type doped layer has a first thickness;

forming a gate electrode on the p-type doped layer;

forming a first passivation layer to cover the gate electrode and the active layer;

forming a field dispersion portion of a field plate on the first passivation layer, wherein a portion of the first passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness;

forming a second passivation layer to cover the field dispersion portion and the first passivation layer;

forming a source via hole and a drain via hole in the second passivation layer and forming a source via hole and a drain via hole in the first passivation layer, the source via hole of the first passivation layer and the source via hole of the second passivation layer together exposing a portion of the active layer, and the drain via hole of the first passivation layer and the drain via hole of the second passivation layer together exposing another portion of the active layer, wherein the p-type doped layer is disposed between the source via holes and the field dispersion portion, the field dispersion portion is disposed between the p-type doped layer and the drain via holes;

forming a source electrode in the source via holes;

forming a drain electrode in the drain via holes;

forming an extending portion of the field plate on the second passivation layer to be electrically connected to the source electrode; and

forming a conductive element of the field plate to electrically connect the field dispersion portion to the extending portion.

15. The manufacturing method of claim 14, wherein the p-type doped layer is made of GaN or AlGaN doped with p-type dopants.

16. The manufacturing method of claim 14, further comprising:

forming a through hole in the second passivation layer to expose the field dispersion portion, wherein the conductive element is formed in the through hole.

17. The manufacturing method of claim 14, further comprising:

forming an insulating layer to cover the field dispersion portion and the first passivation layer;

forming an interlayer portion of the field plate on the insulating layer and above the field dispersion portion, wherein the second passivation layer further covers the insulating layer and the interlayer portion; and

forming a source via hole and a drain via hole in the insulating layer, wherein the source electrode is formed in the source via holes, and the drain electrode is formed in the drain via holes.