METHOD OF FORMING SHALLOW TRENCH ISOLATION AND SEMICONDUCTOR DEVICE

• US 20150364360A1
• Filed: 06/12/2014
• Published: 12/17/2015
• Est. Priority Date: 06/12/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, DE-FANG, TSAI, TENG-CHUN, FU, CHING-FENG, LIN, CHENG-TUNG, WANG, LI-TING, PENG, CHIH-TANG
• Granted Patent: US 9,460,956 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding from the substrate; a second vertical structure protruding from the substrate; an STI between the first vertical structure and the second vertical structure; wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI.

Claims

1. A method of forming a shallow trench isolation between a first vertical structure and a second vertical structure in a substrate, comprising:

providing the substrate;

providing the first vertical structure and the second vertical structure over the substrate;

conformally forming a dielectric layer over the substrate, the first vertical structure, and the second vertical structure;

etching the dielectric layer to expose a portion of the substrate corresponding to the shallow trench isolation;

etching the exposed portion of the substrate to form a recess corresponding to the shallow trench isolation;

removing the dielectric layer; and

forming an oxide layer in the recess as the shallow trench isolation.

2. The method of claim 1, wherein conformally forming the dielectric layer over the substrate, the first vertical structure, and the second vertical structure further comprises conformally forming the dielectric layer by using atomic layer deposition.

3. The method of claim 1, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises anisotropically etching the dielectric layer.

4. The method of claim 1, wherein forming the oxide layer in the recess as the shallow trench isolation further comprises:

forming the oxide layer over the substrate, the first vertical structure, and the second vertical structure by using flowable CVD.

performing CMP on the oxide layer and stopping on the first vertical structure and the second vertical structure; and

etching the oxide layer to expose the substrate and to form the shallow trench isolation.

5. The method of claim 1, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises etching the dielectric layer by using plasma etching.

6. The method of claim 1, wherein etching the exposed portion of the substrate to form the recess corresponding to the shallow trench isolation further comprises etching the exposed portion of the substrate by using plasma etching.

7. The method of claim 1, wherein conformally forming the dielectric layer over the substrate, the first vertical structure, and the second vertical structure further comprises conformally forming the dielectric layer made of silicon nitride.

8. The method of claim 1, wherein conformally forming the dielectric layer over the substrate, the first vertical structure, and the second vertical structure further comprises conformally forming the dielectric layer made of silicon oxide.

9. The method of claim 1, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises etching the dielectric layer to form a first spacer adjacent to the first vertical structure and to form a second spacer adjacent to the second vertical structure, a horizontal width of the first spacer being substantially the same as that of the second spacer.

10. The method of claim 1, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises etching the dielectric layer to form the first spacer having the horizontal width of about 5-20 nanometers.

11. A method of forming a shallow trench isolation in a substrate between first vertical structure and a second vertical structure, comprising:

providing the substrate;

providing the first vertical structure and the second vertical structure over the substrate;

conformally forming a dielectric layer over the substrate, the first vertical structure, and the second vertical structure;

etching the dielectric layer to expose a portion of the substrate corresponding to the shallow trench isolation;

etching the exposed portion of the substrate to form a recess corresponding to the shallow trench isolation;

removing the dielectric layer;

forming an oxide layer over the substrate, the first vertical structure, and the second vertical structure;

performing CMP on the oxide layer and stopping on the first vertical structure and the second vertical structure; and

etching the oxide layer to expose the substrate and to form the shallow trench isolation made of the oxide layer.

12. The method of claim 11, wherein conformally forming the dielectric layer over the substrate, the first vertical structure, and the second vertical structure further comprises conformally forming the dielectric layer by using atomic layer deposition.

13. The method of claim 11, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises anisotropically etching the dielectric layer.

14. The method of claim 11, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises etching the dielectric layer by using plasma etching.

15. The method of claim 11, wherein etching the exposed portion of the substrate to form the recess corresponding to the shallow trench isolation further comprises etching the exposed portion of the substrate by using plasma etching.

16. The method of claim 11, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises etching the dielectric layer to form a first spacer adjacent to the first vertical structure and to form a second spacer adjacent to the second vertical structure, a horizontal width of the first spacer being substantially the same as the second spacer.

17. The method of claim 11, wherein etching the dielectric layer to expose the portion of the substrate corresponding to the shallow trench isolation further comprises etching the dielectric layer to form a first spacer having a horizontal width of 5-20 nanometers adjacent to the first vertical structure and to form a second spacer having a horizontal width of 5-20 nanometers adjacent to the second vertical structure.

18. A semiconductor device, comprising:

a substrate;

a first vertical structure protruding from the substrate;

a second vertical structure protruding from the substrate;

an STI between the first vertical structure and the second vertical structure,

wherein a first horizontal width between the first vertical structure and the STI is substantially the same as a second horizontal width between the second vertical structure and the STI.

19. The device of claim 18, wherein the first horizontal width is about 5-20 nanometers.

20. The device of claim 18, wherein difference between the first horizontal width and the second horizontal width is less than about 1 nanometer.