VHF ETCH BARRIER FOR SEMICONDUCTOR INTEGRATED MICROSYSTEM

• US 20150364363A1
• Filed: 06/17/2014
• Published: 12/17/2015
• Est. Priority Date: 06/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Yi-Hsien, Liang, Kai-Chih, Tsai, Yi Heng, Shen, Wei-Cheng, Cheng, Chun-Ren, Cheng, Chun-Wen, Chiu, Han-Chin, Wu, Tzu-Heng
• Granted Patent: US 9,449,867 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B81B 7/0025 Protection against chemical alteration
• CPC Class Codes: B81B 7/0054 between other parts not provided for in B81B7/0048 - B81B7/0051
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00801 Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer B81C1/00595, B81C1/00468 take precedence
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 24/89 using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Claims

1. An integrated microsystem with a protection barrier structure, comprising:

a first die having a plurality of CMOS devices disposed thereon;

a second die having a plurality of MEMS devices disposed thereon, wherein the second die is bonded to the first die at a bond interface region; and

a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die, wherein the vHF etch barrier structure comprises a vHF etch barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

2. The protection barrier structure of claim 1, wherein the upper surface of the first die comprises a conductive interconnect feature at the bond interface region, and further comprising:

a conductive bonding element extending between the conductive interconnect feature and a MEMS device on the second die;

wherein the stress reduction layer is a conductive material covering the upper surface of the first die at the bond interface region; and

wherein the vHF barrier layer extends over portions of the upper surface of the first die without extending over the bond interface region.

3. The protection barrier structure of claim 1, wherein the stress reduction layer comprises aluminum and the vHF barrier layer comprises a ceramic film.

4. The protection barrier structure of claim 1, wherein the stress reduction layer is disposed onto intersections of sidewall surfaces and lateral surfaces of recesses or bumps disposed along the upper surface of the first die.

5. The protection barrier structure of claim 4, wherein the upper surface of the die comprises a “

V”

shaped sidewall near the bond interface region on which the stress reduction layer is disposed.

6. A semiconductor integrated microsystem comprising:

a first die having a plurality of CMOS devices disposed thereon;

a second die having a plurality of MEMS devices disposed thereon, wherein the second die is bonded to the first die at a bonding interface region; and

a vapor hydrofluoric (vHF) etch barrier structure disposed between the first die and the second die, wherein the vHF etch barrier structure comprises a first barrier layer disposed over an upper surface of the first die, and a second barrier layer disposed over the first barrier layer and covering the upper surface of the first die except at the bonding interface region.

7. The semiconductor integrated microsystem of claim 6, wherein the first barrier layer has a Young'"'"'s modulus smaller than about 120 gigapascals (GPa).

8. The semiconductor integrated microsystem of claim 6, wherein the first barrier layer is a stress-reduction layer to reduce stress due to non-planar surface geometries of at least one of the upper surface of the first die and the second barrier layer for the second barrier layer.

9. The semiconductor integrated microsystem of claim 6, wherein the first die includes an opening which is adjacent to the bonding interface region and through which a conductive interconnect feature on the first die is bonded to the second die, wherein the first barrier layer is disposed on sidewalls of the opening while leaving at least a portion of a bottom surface of the opening uncovered.

10. The semiconductor integrated microsystem of claim 6, wherein the first die includes an opening which is adjacent to the bonding interface region and through which a conductive interconnect feature on the first die is bonded to the second die, wherein the first barrier layer is disposed on sidewalls of the opening and extends continuously over an entire bottom surface of the opening between the sidewalls.

11. The semiconductor integrated microsystem of claim 9, wherein a pair of opposing sidewalls on either side of the bonding interface region exhibit a “

V”

shaped profile.

12. The semiconductor integrated microsystem of claim 6, wherein the second barrier layer comprises a non-conductive material.

13. The semiconductor integrated microsystem of claim 6, wherein the second barrier layer comprises a ceramic film.

14. The semiconductor integrated microsystem of claim 6, wherein the second barrier layer comprises aluminum oxide or aluminum fluoride or aluminum nitride.

15. The semiconductor integrated microsystem of claim 6, wherein the first barrier layer comprises a ductile material.

16. The semiconductor integrated microsystem of claim 6, wherein the first barrier layer comprises multiple layers comprising aluminum (Al), copper (Cu), Titanium (Ti), Tantalum (Ta) or an alloy made of a combination of Al, Cu, Ti and/or Ta.

17. A method of forming a vapor hydrofluoric (vHF) etch barrier structure for a semiconductor integrated microsystem comprising:

forming a trench opening through a dielectric layer of a CMOS wafer to expose a conductive interconnect feature of the CMOS wafer;

forming a first barrier layer over sidewall and bottom surfaces of the trench opening, wherein the first barrier layer abuts the conductive interconnect feature;

forming a second barrier layer over the first barrier layer;

bonding a MEMS wafer to the CMOS wafer through a bonding ring positioned in the trench opening;

forming release openings through substrates of the CMOS wafer and the MEMS wafer; and

applying a vapor Hydrofluoric (vHF) acid through the etch openings to remove a sacrificial layer disposed in the MEMS wafer.

18. The method of claim 17, wherein the conductive interconnect feature is a metal layer of the CMOS wafer.

19. The method of claim 17, wherein the trench opening is formed with a “

V”

shaped sidewall surface.

20. The method of claim 17, further comprising:

forming a second trench through the dielectric layer before bonding the CMOS wafer with the MEMS wafer; and

forming a second dielectric layer over the second barrier layer with a bond opening through the second barrier layer exposing a portion of the first barrier layer at the bottom surface of the trench opening, wherein the bonding ring is formed in the bond opening.