SELF-ALIGNED INTERCONNECT WITH PROTECTION LAYER

• US 20150364371A1
• Filed: 06/12/2014
• Published: 12/17/2015
• Est. Priority Date: 06/12/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Yu-Chan, Fu, Ching-Feng, Lee, Chia-Ying
• Granted Patent: US 10,998,228 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Claims

1. An integrated circuit structure comprising:

a first Inter-Layer Dielectric (ILD);

a gate stack in the first ILD;

a second ILD over the first ILD;

a first contact plug in the second ILD;

a dielectric protection layer on opposite sides of, and in contact with, the first contact plug, wherein the first contact plug and the dielectric protection layer are in the second ILD; and

a dielectric capping layer over and in contact with the first contact plug.

2. The integrated circuit structure of claim 1 further comprising:

a third ILD over the second ILD; and

a second contact plug extending from a top surface of the third ILD to a bottom surface of the second ILD, wherein the second contact plug is electrically coupled to the gate stack.

3. The integrated circuit structure of claim 2, wherein the second contact plug comprises a first bottom surface contacting a top edge of the dielectric protection layer.

4. The integrated circuit structure of claim 1, wherein the first contact plug comprises a bottom surface in contact with a top surface of the first ILD.

5. The integrated circuit structure of claim 1, wherein the dielectric protection layer and the dielectric capping layer are formed of a same dielectric material.

6. The integrated circuit structure of claim 1 further comprising:

a source/drain region;

a third contact plug over and electrically coupled to the source/drain region, wherein the third contact plug is in the first ILD;

a fourth contact plug over and contacting the third contact plug, wherein the fourth contact plug is in the second ILD; and

a fifth contact plug over and in contact with the fourth contact plug, wherein the fifth contact plug extends from a top surface of the third ILD into the second ILD.

7. The integrated circuit structure of claim 6, wherein a bottom surface of the fifth contact plug is substantially coplanar with a top surface of the first contact plug.

8. The integrated circuit structure of claim 1, wherein a top surface of the dielectric capping layer is substantially coplanar with a top surface of the second ILD.

9. An integrated circuit structure comprising:

a first Inter-Layer Dielectric (ILD);

an etch stop layer over the first ILD;

a second ILD over the etch stop layer;

a first slot contact plug in the second ILD, wherein the first slot contact penetrates through the etch stop layer to contact a top surface of the first ILD;

a dielectric protection layer comprising portions on opposite sides of, and in contact with, the first slot contact plug; and

a dielectric capping layer over and in contact with the first slot contact plug, wherein the first slot contact plug, the dielectric protection layer, and the dielectric capping layer are in the second ILD.

10. The integrated circuit structure of claim 9, wherein the dielectric capping layer comprises opposite edges in contact with opposite portions of the dielectric protection layer.

11. The integrated circuit structure of claim 9, wherein a top surface of the dielectric capping layer, a top edge of the dielectric protection layer, and a top surface of the second ILD are substantially coplanar.

12. The integrated circuit structure of claim 9 further comprising:

a first source/drain region under the first ILD;

a gate stack in the first ILD;

a third ILD over the second ILD; and

a gate contact plug in the second ILD and the third ILD.

13. The integrated circuit structure of claim 9 further comprising:

a second source/drain region under the first ILD;

a second slot contact plug over and electrically coupled to the second source/drain region, wherein the second slot contact plug is in the first ILD;

a third slot contact plug over and contacting the second slot contact plug, wherein the second slot contact plug is in the second ILD;

a third ILD over the second ILD; and

a contact plug penetrating through the third ILD, wherein the contact plug is in contact with the third slot contact plug.

14. The integrated circuit structure of claim 13, wherein the contact plug comprises a bottom surface lower than a top surface of the second ILD.

15. A method comprising:

forming a second Inter-Layer Dielectric (ILD) over a first ILD, with a gate stack located in the first ILD;

etching the second ILD to form a first contact opening;

forming a dielectric protection layer on opposite sidewalls of the first contact opening;

forming a first contact plug in the first contact opening, with the first contact plug being between opposite portions of the dielectric protection layer;

forming a dielectric capping layer over and the contacting the first contact plug;

forming a third ILD over the second ILD;

forming a second contact opening in the second ILD and the third ILD; and

filling the second contact opening to form a second contact plug.

16. The method of claim 15, wherein the forming the dielectric capping layer comprises:

recessing the first contact plug to form a recess;

filling the dielectric capping layer in the recess; and

planarizing the dielectric capping layer, wherein a top surface of the dielectric capping layer is substantially level with a top surface of the second ILD.

17. The method of claim 15, wherein in the forming the second contact opening, the dielectric protection layer is exposed to the second contact opening, and wherein the dielectric protection layer is substantially not etched during the forming the second contact opening.

18. The method of claim 15, wherein after the forming the first contact opening, the first ILD is exposed to the first contact opening.

19. The method of claim 15 further comprising:

before the forming the second ILD, forming an etch stop layer over the first ILD, wherein the first contact opening penetrates through the etch stop layer.

20. The method of claim 15 further comprising, when the second contact plug is formed, simultaneously forming a source/drain contact plug in the second ILD and the third ILD.