FAN OUT WAFER LEVEL PACKAGE USING SILICON BRIDGE

• US 20150364422A1
• Filed: 09/26/2014
• Published: 12/17/2015
• Est. Priority Date: 06/13/2014
• Status: Abandoned Application

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Zhai, Jun, Hu, Kunzhong
• Application Number:
  US14/497,495
• Publication Number:
  US 20150364422A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1357 Single coating layer
• CPC Class Codes: H01L 2224/136 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92124 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/381 : Pitch distance

Abstract

A semiconductor device package includes a logic die coupled to a memory die in a side-by-side configuration on a redistribution layer (e.g., the logic die and the memory die are substantially adjacent). A silicon bridge may be used to interconnect the logic die and the memory die. The silicon bridge may be positioned between the die and the redistribution layer. The silicon bridge and the redistribution layer may be coupled to the lower (active) surfaces of the logic die and the memory die. The package may be formed using a wafer level process that forms a plurality of packages simultaneously.

Claims

1. A semiconductor device package, comprising:

a logic die at least partially encapsulated in an encapsulant;

a memory die at least partially encapsulated in the encapsulant, wherein the logic die is substantially adjacent to the memory die in the encapsulant;

a redistribution layer coupled to a lower surface of the logic die and a lower surface of the memory die; and

a silicon bridge interconnecting the logic die and the memory die, wherein the silicon bridge is coupled to the lower surfaces of the logic die and the memory die, and wherein the silicon bridge is located between the die and the redistribution layer.

2. The package of claim 1, wherein the logic die and the memory die are coupled to the redistribution layer in substantially adjacent positions.

3. The package of claim 1, wherein there is at least some encapsulant separating a side surface of the logic die and a side surface of the memory die.

4. The package of claim 1, wherein the logic die is coupled to the silicon bridge using a plurality of terminals coupled to traces in the silicon bridge, wherein the traces have an interconnect trace pitch of at most about 1 μ

m.

5. The package of claim 1, wherein the memory die is coupled to the silicon bridge using a plurality of terminals coupled to traces in the silicon bridge, wherein the traces have an interconnect trace pitch of at most about 1 μ

m.

6. The package of claim 1, wherein the lower surfaces of the logic die and the memory die comprise active surfaces of the die, and wherein the silicon bridge and the redistribution layer are directly attached to the active surfaces.

7. The package of claim 1, further comprising one or more terminals coupling the logic die and the memory die to the redistribution layer.

8. The package of claim 1, wherein the silicon bridge is located in a recess in the redistribution layer, and portions of the lower surfaces of the logic die and the memory die are in direct contact with routing in the redistribution layer.

9. A method for forming a semiconductor device package, comprising:

placing a logic die and a memory die substantially adjacent to each other on a carrier;

coupling a silicon bridge to the logic die and the memory die, wherien the silicon bridge interconnects the logic die and the memory die;

at least partially encapsulating the logic die, the memory die, and the silicon bridge in an encapsulant;

removing the carrier from the logic die and the memory die; and

coupling the logic die and the memory die to a redistribution layer.

10. The method of claim 9, further comprising coupling the silicon bridge to the logic die using a first set of terminals coupled to traces in the silicon bridge, and coupling silicon bridge to the memory die using a second set of terminals coupled to traces in the silicon bridge, wherein the traces in the silicon bridge have an interconnect trace pitch of at most about 1 μ

m.

11. The method of claim 9, wherein there is at least some space between the logic die and the memory die on the carrier, and wherein at least some encapsulant fills the space between the logic die and the memory die.

12. The method of claim 9, further comprising forming one or more terminals on the logic die and the memory die, and coupling the logic die and the memory die to the redistribution layer using the terminals.

13. The method of claim 12, wherein the terminals are formed on the logic die and the memory die before placing the die on the carrier.

14. The method of claim 9, further comprising forming a plurality of terminals on a surface of the redistribution layer opposite the logic die and the memory die, wherein at least one of the terminals is coupled to the logic die through routing in the redistribution layer, and wherein at least one of the terminals is coupled to the memory die through routing in the redistribution layer.

15. A semiconductor device package, comprising:

a redistribution layer;

a logic die coupled to a first surface of the redistribution layer and at least partially encapsulated in an encapsulant;

a memory die coupled to the first surface of the redistribution layer and at least partially encapsulated in the encapsulant, wherein the logic die is substantially adjacent to the memory die on the first surface of the redistribution layer; and

a silicon bridge interconnecting the logic die and the memory die, wherein the silicon bridge is located between the first surface of the redistribution layer and the die.

16. The package of claim 15, wherein the redistribution layer comprises a polymer with two or more layers of routing that redistributes connections on one side of the redistribution layer to another horizontally displaced location on the other side of the redistribution layer.

17. The package of claim 15, wherein the redistribution layer comprises a thickness between about 10 μ

m and about 50 μ

m.

18. The package of claim 15, wherein the silicon bridge has a thickness of at most about 10 μ

m.

19. The package of claim 15, wherein an upper surface of the logic die and an upper surface of the memory die are encapsulated in the encapsulant.

20. The package of claim 15, further comprising at least one terminal coupled to the redistribution layer through the encapsulant, wherein the terminal is configured to couple the redistribution layer to another semiconductor device package.