SPLIT GATE FLASH MEMORY STRUCTURE AND METHOD OF MAKING THE SPLIT GATE FLASH MEMORY STRUCTURE

• US 20150364558A1
• Filed: 06/17/2014
• Published: 12/17/2015
• Est. Priority Date: 06/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Liu, Shih-Chang
• Granted Patent: US 9,614,048 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 2924/1438 Flash memory
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate located over the semiconductor substrate between the source and drain regions. The floating gate is arranged between the word line and the erase gate. Even more, the semiconductor structure includes a dielectric disposed between the erase and floating gates. A thickness of the dielectric between the erase and floating gates is variable and increases towards the semiconductor substrate. A method of manufacturing the semiconductor structure is also provided.

Claims

1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including a source region and a drain region;

a floating gate, a word line, and an erase gate located over the semiconductor substrate, wherein the floating gate and the word line are located between the source and drain regions, and wherein the floating gate is arranged between the word line and the erase gate; and

a dielectric structure disposed between the erase and floating gates, wherein a thickness of the dielectric structure between the erase and floating gates is variable and increases towards the semiconductor substrate.

2. The semiconductor structure according to claim 1, wherein the dielectric structure includes a bottom region and a top region located atop the bottom region, the bottom region including a bottom surface approximately coplanar with a bottom surface of the floating gate and a first thickness greater than a second thickness of the top region, and the top region including a top surface approximately coplanar with a top surface of the floating gate.

3. The semiconductor structure according to claim 2, wherein the second thickness of the top region is about 40-60 Angstroms (A) and the first thickness of the bottom region is greater than about 100 A.

4. The semiconductor structure according to claim 2, wherein the second thickness of the top region is uniform and the first thickness of the bottom region is uniform.

5. The semiconductor structure according to claim 2, wherein the floating gate comprises a planar sidewall abutting the bottom region and the top region, and wherein the erase gate comprises a non-planar sidewall abutting the bottom region and the top region.

6. The semiconductor structure according to claim 1, further including:

a base dielectric region arranged between the semiconductor substrate and the floating and erase gates, wherein the dielectric structure vertically extends from the base dielectric region.

7. The semiconductor structure according to claim 1, wherein the floating gate includes a ledge adjacent to the erase gate, the ledge being a recess in a top surface of the floating gate, and the dielectric structure extending to the ledge from a position approximately even with a bottom surface of the floating gate.

8. The semiconductor structure according to claim 1, further including:

a control gate disposed above the floating gate; and

a second dielectric structure disposed between the control gate and the floating gate.

9. The semiconductor structure according to claim 1, wherein the semiconductor substrate further includes:

a second floating gate and a second word line spaced between the source region and a second drain region, wherein the second floating gate is between the second word line and the erase gate; and

a second dielectric structure disposed between the erase gate and the second floating gate, wherein a thickness of the second dielectric structure between the erase gate and the second floating gate is variable and increases towards the semiconductor substrate.

10-19. -19. (canceled)

20. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including a shared source/drain region and two individual source/drain regions, the shared and individual source/drain regions spaced along a surface of the semiconductor substrate with the shared source/drain region between the two individual source/drain regions; and

two split gate memory cells disposed between the the two individual source/drain regions, wherein one of the split gate memory cells includes;

a floating gate, a word line, and an erase gate spaced over the surface, wherein the floating gate and the word line are arranged between the shared source/drain region and a corresponding individual source/drain region, and wherein the floating gate is arranged between the word line and the erase gate; and

a dielectric structure disposed between the erase and floating gates,

wherein a thickness of the dielectric structure between the erase and floating gates is variable and increases towards the semiconductor substrate.

21. The semiconductor structure according to claim 20, wherein the dielectric structure includes a bottom region and a top region located atop the bottom region, the bottom region including a bottom surface approximately coplanar with a bottom surface of the floating gate and a first thickness greater than a second thickness of the top region, and the top region including a top surface approximately coplanar with a top surface of the floating gate.

22. The semiconductor structure according to claim 21, wherein the second thickness of the top region is uniform and the first thickness of the bottom region is uniform.

23. The semiconductor structure according to claim 21, wherein the floating gate comprises a planar sidewall abutting the top and bottom regions, and wherein the erase gate comprises a non-planar sidewall abutting the top and bottom regions.

24. The semiconductor structure according to claim 20, further comprising:

a base dielectric region arranged between the semiconductor substrate and the floating and erase gates, wherein the dielectric structure extends from the base dielectric region in a direction normal to the base dielectric region.

25. The semiconductor structure according to claim 20, wherein the floating gate includes a ledge adjacent to the erase gate, the ledge being a recess in a top surface of the floating gate, and wherein the dielectric structure extends to the ledge from a position approximately even with a bottom surface of the floating gate.

26. The semiconductor structure according to claim 20, further comprising:

a control gate disposed above the floating gate; and

a second dielectric structure disposed between the control gate and the floating gate.

27. A memory cell comprising:

a word line, a floating gate, and an erase gate laterally spaced over a semiconductor substrate with the floating gate arranged between the word line and the erase gate;

a dielectric structure arranged between the erase and floating gates, wherein a thickness of the dielectric structure increases from an upper surface of the floating gate to a lower surface of the floating gate; and

a control gate arranged over the floating gate.

28. The memory cell according to claim 27, wherein the dielectric structure comprises a lower region and an upper region arranged between the upper and lower surfaces of the floating gate, and wherein a thickness of the upper region is less than a thickness of the lower region.

29. The memory cell according to claim 27, wherein a width of the erase gate tapers at an interface with the dielectric structure.

30. The memory cell according to claim 27, wherein upper surfaces of the word line, the control gate, and the erase gate are substantially coplanar.