SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURE

• US 20150364560A1
• Filed: 06/13/2014
• Published: 12/17/2015
• Est. Priority Date: 06/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, CHIH-HAO, LIEN, WAI-YI, JU, SHI-NING, YANG, KAI-CHIEH, LAN, WEN-TING
• Granted Patent: US 9,755,033 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Claims

1. A method of forming a vertical structure, comprising:

providing a substrate;

providing the vertical structure having a drain over the substrate;

forming a metal layer over a top and at least a portion of a sidewall of the drain of the vertical structure; and

annealing the metal layer to form silicide over the top and the sidewall of the drain of the vertical structure.

2. The method of claim 1, wherein providing the vertical structure having the drain over the substrate further comprises providing the vertical structure having a source, a channel, and the drain.

3. The method of claim 2, further comprising:

shrinking the source, the channel, and the drain by oxidation;

removing oxidized portions of the source, the channel, and the drain;

forming silicide over the source;

forming a first interlayer dielectric over the source;

forming a high-k dielectric layer over the channel;

forming a metal gate layer over the high-k dielectric layer;

forming a second interlayer dielectric over the metal gate layer; and

forming an etch stop layer to cover a portion of the sidewall of the drain.

4. The method of claim 3, wherein forming the etch stop layer to cover the portion of the sidewall of the drain further comprises:

forming the etch stop layer over the sidewall of the drain; and

etching back the etch stop layer to expose a portion of the sidewall of the drain.

5. The method of claim 3, wherein shrinking the source, the channel, and the drain by oxidation further comprises shrinking the source, the channel, and the drain to have a same width of about 4-10 nanometers.

6. The method of claim 3, wherein forming the metal layer over the top and the sidewall of the drain of the vertical structure further comprises forming the metal layer over a upper portion of the sidewall of the drain of the vertical structure.

7. A method of forming a vertical structure, comprising:

providing a substrate;

providing the vertical structure having a source, a channel, and a drain over the substrate;

shrinking the source and the channel by oxidation;

forming a metal layer over the drain of the vertical structure; and

annealing the metal layer to form a silicide over the drain of the vertical structure.

8. The method of claim 7, wherein providing the vertical structure having the source, the channel, and the drain over the substrate further comprises providing the vertical structure having a hard mask over the drain for protecting a top of the drain.

9. The method of claim 8, wherein shrinking the source and the channel by oxidation further comprises:

forming a first oxide layer over the vertical structure;

forming a nitride layer over the first oxide layer;

forming a second oxide layer over the nitride layer;

performing CMP on the first oxide layer and the second oxide layer and stopping at a portion of the nitride layer;

etching the nitride layer and the first oxide layer to expose the drain;

forming a spacer adjacent to the drain;

etching the first oxide layer to expose the channel and the source;

shrinking the source and the channel substantially without shrinking the drain covered by the hard mask and the spacer;

removing the spacer; and

removing oxidized portions of the source and the channel.

10. The method of claim 7, further comprising:

forming silicide over the source;

forming a first interlayer dielectric over the source;

forming a high-k dielectric layer over the channel;

forming a metal gate layer over the high-k dielectric layer;

forming a second interlayer dielectric over the metal gate layer; and

forming an etch stop layer to cover a portion of the sidewall of the drain.

11. The method of claim 7, wherein providing the vertical structure having the source, the channel, and the drain over the substrate further comprises providing the source, the channel, and the drain to have the same width of about 10-20 nanometers.

12. The method of claim 7, wherein shrinking the source and the channel by oxidation further comprises shrinking the source and the channel to have the same width of about 4-10 nanometers.

13. The method of claim 7, wherein forming the metal layer over the drain of the vertical structure further comprises forming a metal layer over a top of the drain of the vertical structure.

14. The method of claim 13, wherein annealing the metal layer to form silicide over the drain of the vertical structure further comprises annealing the metal layer to form silicide over the top of the drain of the vertical structure.

15. The method of claim 7, wherein forming the metal layer over the drain of the vertical structure further comprises forming a metal layer over a top and a sidewall of the drain of the vertical structure.

16. The method of claim 15, wherein annealing the metal layer to form silicide over the drain of the vertical structure further comprises annealing the metal layer to form silicide over the top and the sidewall of the drain of the vertical structure.

17. A semiconductor device, comprising:

a substrate;

a vertical device over the substrate and having a drain; and

a silicide over a top and at least a portion of a sidewall of the drain of the vertical structure.

18. The semiconductor device of claim 17, wherein the vertical device further comprises a channel and a source, wherein each of the source, the channel, and the drain has a same width.

19. The semiconductor device of claim 17, wherein the vertical device further comprises a channel and a source having a same width, wherein the drain has a width different from the width of the channel.

20. The semiconductor device of claim 17, wherein the vertical device further comprises a channel and a source having the width of about 4-10 nanometers, wherein the drain has the width of about 10-20 nanometers.