REPLICATING LOGIC BLOCKS TO ENABLE INCREASED THROUGHPUT

• US 20150370574A1
• Filed: 06/22/2015
• Published: 12/24/2015
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Original Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Inventors: Jackson, Hugh
• Granted Patent: US 11,709,682 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06F 9/3875 Pipelining a single stage, e.g. superpipelining

Abstract

A datapath pipeline which uses replicated logic blocks to increase the throughput of the pipeline is described. In an embodiment, the pipeline, or a part thereof, comprises a number of parallel logic paths each comprising the same logic. Input register stages at the start of each logic path are enabled in turn on successive clock cycles such that data is read into each logic path in turn and the logic in the different paths operates out of phase. The output of the logic paths is read into one or more output register stages and the logic paths are combined using a multiplexer which selects an output from one of the logic paths on any clock cycle. Various optimization techniques are described and in various examples, register retiming may also be used. In various examples, the datapath pipeline is within a processor.

Claims

1. A datapath pipeline comprising:

one or more replicated blocks of logic forming parallel logic paths within the pipeline;

an input register block at a start of each logic path, wherein in any clock cycle only a subset of the input register blocks are enabled;

a multiplexer arranged to recombine the parallel logic paths into a single output; and

a single output register block connected to the output of the multiplexer.

2. A pipeline according to claim 1, wherein a replicated block of logic comprises hardware logic which takes more than one clock cycle to complete.

3. A pipeline according to claim 1, further comprising:

a block of logic between the multiplexer and an output register block.

4. A pipeline according to claim 1, further comprising:

an intermediate multiplexer connected to a subset of the logic paths and arranged to combine the subset of the logic paths into a single output.

5. A pipeline according to claim 4, further comprising:

a block of logic between the intermediate multiplexer and the multiplexer.

6. A pipeline according to claim 1, wherein each logic path comprises a first block of logic and a second block of logic and an intermediate register stage between the first block of logic and the second block of logic.

7. A pipeline according to claim 1, comprising register stages at only the input and output of the pipeline.

8. A pipeline according to claim 1, wherein the pipeline is within a functional unit of a processor.

9. A method of operating a datapath pipeline, the method comprising:

enabling each of a set of input register blocks in turn on successive clock cycles to pass data into a plurality of parallel logic paths;

processing the data in each logic path over a plurality of clock cycles;

using a multiplexer to select an output from each logic path in turn on successive clock cycles; and

enabling a single output register block connected to an output of the multiplexer on all clock cycles.

10. A method according to claim 9, wherein the datapath pipeline is within a functional unit of a processor.

11. A method of designing a datapath pipeline, the pipeline comprising logic and the method comprising:

replicating at least a part of the logic to form multiple logic paths;

adding an input register block to a start of each logic path;

adding an output register block to an end of each logic path;

configuring the pipeline to enable the input register blocks in sequence on successive clock cycles;

configuring the pipeline to enable the output register blocks in sequence on successive clock cycles;

adding a multiplexer to combine outputs from the logic paths; and

replacing the output register block at the end of two or more logic paths with a single output register block positioned after a multiplexer combining outputs from the two or more logic paths.

12. A method according to claim 11, further comprising:

using pipelining to optimize each logic path.

13. A method according to claim 11, further comprising:

replacing a portion of the replicated logic at the end of two or more logic paths with a single instance of the portion of replicated logic positioned after a multiplexer combining outputs from the two or more logic paths.

14. A method according to claim 11, further comprising:

replacing a portion of the replicated logic in two or more logic paths with a single instance of the portion of replicated logic and a multiplexer combining outputs from the two or more logic paths.

15. A method according to claim 11, further comprising:

optimizing a position of the one or more multiplexers in the pipeline using a register retiming algorithm.

16. A method according to claim 15, wherein the register retiming algorithm is one of a network flow algorithm and a mixed-integer linear program algorithm.

17. A method according to claim 11, wherein the datapath pipeline is within a functional unit of a processor.