REPLICATING LOGIC BLOCKS TO ENABLE INCREASED THROUGHPUT
First Claim
1. A datapath pipeline comprising:
- one or more replicated blocks of logic forming parallel logic paths within the pipeline;
an input register block at a start of each logic path, wherein in any clock cycle only a subset of the input register blocks are enabled;
a multiplexer arranged to recombine the parallel logic paths into a single output; and
a single output register block connected to the output of the multiplexer.
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Abstract
A datapath pipeline which uses replicated logic blocks to increase the throughput of the pipeline is described. In an embodiment, the pipeline, or a part thereof, comprises a number of parallel logic paths each comprising the same logic. Input register stages at the start of each logic path are enabled in turn on successive clock cycles such that data is read into each logic path in turn and the logic in the different paths operates out of phase. The output of the logic paths is read into one or more output register stages and the logic paths are combined using a multiplexer which selects an output from one of the logic paths on any clock cycle. Various optimization techniques are described and in various examples, register retiming may also be used. In various examples, the datapath pipeline is within a processor.
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Citations
17 Claims
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1. A datapath pipeline comprising:
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one or more replicated blocks of logic forming parallel logic paths within the pipeline; an input register block at a start of each logic path, wherein in any clock cycle only a subset of the input register blocks are enabled; a multiplexer arranged to recombine the parallel logic paths into a single output; and a single output register block connected to the output of the multiplexer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of operating a datapath pipeline, the method comprising:
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enabling each of a set of input register blocks in turn on successive clock cycles to pass data into a plurality of parallel logic paths; processing the data in each logic path over a plurality of clock cycles; using a multiplexer to select an output from each logic path in turn on successive clock cycles; and enabling a single output register block connected to an output of the multiplexer on all clock cycles. - View Dependent Claims (10)
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11. A method of designing a datapath pipeline, the pipeline comprising logic and the method comprising:
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replicating at least a part of the logic to form multiple logic paths; adding an input register block to a start of each logic path; adding an output register block to an end of each logic path; configuring the pipeline to enable the input register blocks in sequence on successive clock cycles; configuring the pipeline to enable the output register blocks in sequence on successive clock cycles; adding a multiplexer to combine outputs from the logic paths; and replacing the output register block at the end of two or more logic paths with a single output register block positioned after a multiplexer combining outputs from the two or more logic paths. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification