MEMORY MODULE CONTROLLER SUPPORTING EXTENDED WRITES

• US 20150370655A1
• Filed: 03/15/2013
• Published: 12/24/2015
• Est. Priority Date: 03/15/2013
• Status: Abandoned Application

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Tucek, Joseph A., Lillibridge, Mark David, Golab, Wojciech
• Application Number:
  US14/764,609
• Publication Number:
  US 20150370655A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2201/82 Solving problems relating to consistency
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Example methods and apparatus disclose supporting extended writes to a memory. An example method disclosed herein includes storing recovery information associated with a write request in a memory without processor intervention, the recovery information to facilitate redoing or undoing a write requested by the write request in the event that the write is interrupted, the write request received from a processor and comprising a destination address and new data; and if the write is not interrupted, writing the new data to the destination address in the memory without processor intervention

Claims

1. A method comprising:

storing recovery information associated with a write request in a memory without processor intervention, the recovery information to facilitate redoing or undoing a write requested by the write request in the event that the write is interrupted, the write request received from a processor and comprising a destination address and new data; and

if the write is not interrupted, writing the new data to the destination address in the memory without processor intervention.

2. A method according to claim 1, wherein storing the recovery information without processor intervention comprises storing the recovery information in a non-volatile log of the memory without processor intervention.

3. A method according to claim 1, further comprising:

after a system crash or a power failure that interrupts the write, performing at least one of redoing the write or undoing the write based on the recovery information without processor intervention.

4. A method according to claim 2, further comprising:

if the write is interrupted, using the recovery information to write the new data to the destination address in the memory without processor intervention.

5. A method according to claim 1, further comprising:

after an interruption of the write, providing the recovery information to the processor for use in undoing or redoing the write.

6. An apparatus comprising:

a bus interface to receive a write request from a processor to write to a memory comprising a destination address and new data; and

a logic circuit to cause storing of recovery information associated with the write request, the recovery information to facilitate redoing or undoing a write associated with the write request in the event that the write is interrupted.

7. An apparatus according to claim 6, wherein, if the write is not interrupted, the logic circuit is further configured to:

write the new data to the destination address in the memory, and

erase the recovery information without processor intervention after the new data is written to the destination address.

8. An apparatus according to claim 6, wherein the logic circuit is further configured to:

store the destination address and new data as the recovery information; and

after an interruption of an attempt to perform a memory access operation of the write request, write the new data to the destination address in the memory.

9. An apparatus according to claim 6, wherein the logic circuit is further configured to:

read the contents in the memory of the destination address;

store the destination address and the read contents as the recovery information; and

after an interruption of the write, write the read contents to the destination address in the memory.

10. An apparatus according to claim 6, wherein the logic circuit and the bus interface are collocated in a memory module of the memory.

11. An apparatus according to claim 6, wherein the recovery information is stored in a log in the memory.

12. A tangible computer readable storage medium comprising instructions that, when executed, cause a machine to at least:

issue a write request comprising a destination address and new data to a memory module,

wherein, in response to receiving the write request, the memory module stores recovery information associated with the write request to facilitate undoing the write or redoing the write in the event of an interruption of the write.

13. An apparatus comprising:

a bus interface to receive a copy-on-write write command from a processor, the copy-on-write write command comprising a first address, a second address, and modification data; and

a logic circuit to read first data from the first address in a memory, update the first data using the modification data, and store the updated data at the second address in the memory.

14. An apparatus according to claim 13, wherein the modification data comprises an offset and new data, and the logic circuit is further to update the first data using the modification data by replacing first data at the offset with the new data.

15. An apparatus according to claim 13, wherein the logic circuit is further to update the first data using the modification data by at least one of inserting new data at a first offset in the first data or deleting data at a second offset in the first data.

16. An apparatus according to claim 13, wherein a length of the first data is determined by at least one of a predetermined value, a length field of the copy-on-write write command, or a difference between the first address and a third address of the copy-on-write write command.

17. An apparatus according to claim 13, wherein the logic circuit and the bus interface are collocated in a memory module of the memory.

18. A method comprising:

reading first data from a first address in a memory without processor intervention, the first address specified in a copy-on-write write command received from a processor;

updating the first data using modification data of the copy-on-write write command without processor intervention; and

storing the updated data at a second address of the copy-on-write write command in the memory without processor intervention.

19. A method according to claim 18, wherein the modification data comprises an offset and new data, and the method further comprising updating the first data using the modification data by replacing first data at the offset with the new data.

20. A method according to claim 18, further comprising updating the first data using the modification data by least one of inserting new data at a first offset of the first data or deleting old data at a second offset of the first data.

21. A method according to claim 18, wherein a length of the first data is determined by at least one of a predetermined value, a length field of the copy-on-write write command, or a difference between the first address and a third address of the copy-on-write write command.

22. A tangible computer readable storage medium comprising instructions that, when executed, cause a machine to at least:

send a copy-on-write write request to a memory module, the copy-on-write write request comprising a first address, a second address, and modification data,

wherein, in response to receiving the write request, the memory module reads first data from the first address in a memory, updates the first data using the modification data, and stores the updated data at the second address in the memory.